JPS599620U - Graphic equalizer circuit - Google Patents

Graphic equalizer circuit

Info

Publication number
JPS599620U
JPS599620U JP10385582U JP10385582U JPS599620U JP S599620 U JPS599620 U JP S599620U JP 10385582 U JP10385582 U JP 10385582U JP 10385582 U JP10385582 U JP 10385582U JP S599620 U JPS599620 U JP S599620U
Authority
JP
Japan
Prior art keywords
resistor
cut
variable resistors
differential amplifier
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10385582U
Other languages
Japanese (ja)
Inventor
奥村　八郎
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP10385582U priority Critical patent/JPS599620U/en
Publication of JPS599620U publication Critical patent/JPS599620U/en
Pending legal-status Critical Current

Links

Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Networks Using Active Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のグラフィックイコライザ回路を示す回路
図、第２図は本考案の一実施例を示す回路図、及び第３
図はその周波数設定回路の等価回路図である。 主な図番の説明、１２・・・差動増幅器、１５・・・カ
ット量設定抵抗、１６．　１７．　１８．　１９．　２
０・・・可変抵抗、２１・・・周波数設定回路。Fig. 1 is a circuit diagram showing a conventional graphic equalizer circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is a circuit diagram showing an embodiment of the present invention.
The figure is an equivalent circuit diagram of the frequency setting circuit. Explanation of main figure numbers, 12... Differential amplifier, 15... Cut amount setting resistor, 16. 17. 18. 19. 2
0...Variable resistor, 21...Frequency setting circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第１入力端子に入力信号が、第２入力端子に出力端子か
らの負帰還信号が、帰還抵抗を介してそれぞれ印加され
る差動増幅器と、該差動増幅器の出力信号路に挿入され
たカット量設定抵抗と、前記差動増幅器の第２入力端子
と前記カット量設定抵抗の一端との間に挿入された中点
アース型の複数の可変抵抗と、該可変抵抗の可動接点の
それぞれに接続された周波数設定回路とから成り、前記
帰還抵抗と前記可変抵抗のそれぞれとによって周波数毎
にブースト量を定めるとともに、前記カット量設定抵抗
と前記可変抵抗のそれぞれとによって周波数毎のカット
量を定める様に成したグラフィックイコライザ回路。A differential amplifier to which an input signal is applied to a first input terminal and a negative feedback signal from an output terminal is applied to a second input terminal via a feedback resistor, and a cut inserted in an output signal path of the differential amplifier. an amount setting resistor, a plurality of midpoint ground type variable resistors inserted between a second input terminal of the differential amplifier and one end of the cut amount setting resistor, and a movable contact of the variable resistors each connected to the plurality of variable resistors. and a frequency setting circuit configured to determine the amount of boost for each frequency by each of the feedback resistor and the variable resistor, and determine the amount of cut for each frequency by each of the cut amount setting resistor and each of the variable resistors. A graphic equalizer circuit created in this way.
JP10385582U 1982-07-08 1982-07-08 Graphic equalizer circuit Pending JPS599620U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10385582U JPS599620U (en) 1982-07-08 1982-07-08 Graphic equalizer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10385582U JPS599620U (en) 1982-07-08 1982-07-08 Graphic equalizer circuit

Publications (1)

Publication Number Publication Date
JPS599620U true JPS599620U (en) 1984-01-21

Family

ID=30244115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10385582U Pending JPS599620U (en) 1982-07-08 1982-07-08 Graphic equalizer circuit

Country Status (1)

Country Link
JP (1) JPS599620U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01201503A (en) * 1988-02-01 1989-08-14 Asahi Chem Ind Co Ltd Improved disposable sanitary material
JPH0455823U (en) * 1990-09-17 1992-05-13

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132009A (en) * 1980-03-21 1981-10-16 Nippon Atsudenki Kk Tone control device
JPS5717219A (en) * 1980-07-05 1982-01-28 Nippon Gakki Seizo Kk Resonance circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132009A (en) * 1980-03-21 1981-10-16 Nippon Atsudenki Kk Tone control device
JPS5717219A (en) * 1980-07-05 1982-01-28 Nippon Gakki Seizo Kk Resonance circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01201503A (en) * 1988-02-01 1989-08-14 Asahi Chem Ind Co Ltd Improved disposable sanitary material
JPH0446147B2 (en) * 1988-02-01 1992-07-29 Asahi Chemical Ind
JPH0455823U (en) * 1990-09-17 1992-05-13

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