JPS58516U - Graphic equalizer circuit - Google Patents

Graphic equalizer circuit

Info

Publication number
JPS58516U
JPS58516U JP9453381U JP9453381U JPS58516U JP S58516 U JPS58516 U JP S58516U JP 9453381 U JP9453381 U JP 9453381U JP 9453381 U JP9453381 U JP 9453381U JP S58516 U JPS58516 U JP S58516U
Authority
JP
Japan
Prior art keywords
variable resistor
amplifier
terminal
equalizer circuit
variable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9453381U
Other languages
Japanese (ja)
Other versions
JPS6342594Y2 (en
Inventor
梶原　芳史
Original Assignee
日本ビクター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本ビクター株式会社 filed Critical 日本ビクター株式会社
Priority to JP9453381U priority Critical patent/JPS58516U/en
Publication of JPS58516U publication Critical patent/JPS58516U/en
Application granted granted Critical
Publication of JPS6342594Y2 publication Critical patent/JPS6342594Y2/ja
Granted legal-status Critical Current

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  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図Ａ、　Ｂは夫々従来の各側を示す回路図、第２図
は利得調整回路を有する従来のグラフィック・イルライ
ザ回路の一例の要部を示す回路図、第３図は本考案の一
実施例の要部を示す回路図である。 １・・・・・・入力端子、２・・・・・・演算増幅器、
３・・・・・・増幅器、４１〜４、・・・・・・共振回
路、５・・・・・・出力端子、ＶＲ１〜ＶＲｎ−・・・
・・可変抵抗器。1A and 1B are conventional circuit diagrams showing each side, FIG. 2 is a circuit diagram showing the main part of an example of a conventional graphic enhancer circuit having a gain adjustment circuit, and FIG. FIG. 2 is a circuit diagram showing main parts of the embodiment. 1...Input terminal, 2...Operation amplifier,
3...Amplifier, 41-4...Resonance circuit, 5...Output terminal, VR1-VRn-...
...Variable resistor.

Claims (1)

【実用新案登録請求の範囲】 １　人力信号を増幅する増幅器と、該増幅器の入力端子
に第１の固定端子が接続されｉ増幅器の出力端子に第２
の固定端子が接続されると共に中点タップ端子が接地さ
れてなる可変抵抗器の複数個からなる第１の可変抵抗器
群と、該増幅器の入力端子に第２の固定端子が接続され
該増幅器の出力端子に第１の固定端子が接続されると共
に中点タップ端子が接地されてなる可変抵抗器の複数個
からなる第２の可変抵抗器群と、互いに独立に摺動せし
められる該第１及び第２の可変抵抗器群の夫々の摺動子
に各別に接続されており、上記入力信号に対し準数の分
割周波数帯域毎にレベル制御を行なうために互いに共振
周波数が異ならしめられた複数個の共振回路とから構成
したグラフィック・イコライザ回路。 ２　該第１及び第２の可変抵抗器群は、夫々略同数の可
変抵抗器から構成されてなる実用新案登録請求の範囲第
１項記載のグラフィック・イコライザ回路。[Claims for Utility Model Registration] 1. An amplifier for amplifying a human power signal, a first fixed terminal connected to the input terminal of the amplifier, and a second fixed terminal connected to the output terminal of the amplifier.
a first variable resistor group consisting of a plurality of variable resistors to which fixed terminals are connected and whose center tap terminals are grounded; and a second fixed terminal connected to the input terminal of the amplifier. a second variable resistor group consisting of a plurality of variable resistors in which a first fixed terminal is connected to the output terminal of the variable resistor and a center tap terminal is grounded; and a plurality of resistors each having a different resonant frequency, each of which is connected to each slider of the second variable resistor group, and has a different resonant frequency in order to control the level of the input signal for each quasi-divided frequency band. A graphic equalizer circuit consisting of several resonant circuits. 2. The graphic equalizer circuit according to claim 1, wherein the first and second variable resistor groups each include substantially the same number of variable resistors.
JP9453381U 1981-06-25 1981-06-25 Graphic equalizer circuit Granted JPS58516U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9453381U JPS58516U (en) 1981-06-25 1981-06-25 Graphic equalizer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9453381U JPS58516U (en) 1981-06-25 1981-06-25 Graphic equalizer circuit

Publications (2)

Publication Number Publication Date
JPS58516U true JPS58516U (en) 1983-01-05
JPS6342594Y2 JPS6342594Y2 (en) 1988-11-08

Family

ID=29889456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9453381U Granted JPS58516U (en) 1981-06-25 1981-06-25 Graphic equalizer circuit

Country Status (1)

Country Link
JP (1) JPS58516U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6091706A (en) * 1983-10-25 1985-05-23 Rohm Co Ltd Amplifier circuit
JPS6340409U (en) * 1986-09-01 1988-03-16
JPH04132729U (en) * 1992-04-22 1992-12-09 日本コロムビア株式会社 Frequency characteristic adjustment circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721689A (en) * 1980-07-15 1982-02-04 Matsushita Electric Works Ltd Heat insulated window frame material

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721689A (en) * 1980-07-15 1982-02-04 Matsushita Electric Works Ltd Heat insulated window frame material

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6091706A (en) * 1983-10-25 1985-05-23 Rohm Co Ltd Amplifier circuit
JPS6340409U (en) * 1986-09-01 1988-03-16
JPH04132729U (en) * 1992-04-22 1992-12-09 日本コロムビア株式会社 Frequency characteristic adjustment circuit

Also Published As

Publication number Publication date
JPS6342594Y2 (en) 1988-11-08

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