JPS599617U - amplifier circuit - Google Patents
amplifier circuitInfo
- Publication number
- JPS599617U JPS599617U JP10366182U JP10366182U JPS599617U JP S599617 U JPS599617 U JP S599617U JP 10366182 U JP10366182 U JP 10366182U JP 10366182 U JP10366182 U JP 10366182U JP S599617 U JPS599617 U JP S599617U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- operational amplifier
- amplifier
- recorded
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は出力電流を増強する構成の。
演算増幅器を用いた増幅回路の従来例を示す図、第３図
は本考案の一実施例の増幅回路を示す図、第４図は本考
案の他の実施例の増幅回路を示す図である。
ｏｐｌ、 ｏｐ１’ 、 ｏｐ２は演算増幅器、Ｒ１，
Ｒ２，Ｒ３゜Ｒ４，Ｒ□′及びＲ２／は抵抗、Ｑ□＋
Ｑ２はトランジスタ、Ｄはダイオード、Ｃはコンデンサ
、１は入力端子、２は出力端子である。FIGS. 1 and 2 show configurations for increasing the output current. FIG. 3 is a diagram showing a conventional example of an amplifier circuit using an operational amplifier, FIG. 3 is a diagram showing an amplifier circuit according to one embodiment of the present invention, and FIG. 4 is a diagram showing an amplifier circuit according to another embodiment of the present invention. . opl, op1', op2 are operational amplifiers, R1,
R2, R3゜R4, R□' and R2/ are resistances, Q□+
Q2 is a transistor, D is a diode, C is a capacitor, 1 is an input terminal, and 2 is an output terminal.
Claims (1)
てボルテージフオ占アとしてカスケードに接続した第２
の演算増幅器とを有する増幅回路。a first operational amplifier; and a second operational amplifier connected in cascade as a voltage converter to the output of the first operational amplifier.
An amplifier circuit having an operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10366182U JPS599617U (en) | 1982-07-07 | 1982-07-07 | amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10366182U JPS599617U (en) | 1982-07-07 | 1982-07-07 | amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS599617U true JPS599617U (en) | 1984-01-21 |
Family
ID=30243741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10366182U Pending JPS599617U (en) | 1982-07-07 | 1982-07-07 | amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS599617U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5850715B2 (en) * | 1981-10-13 | 1983-11-11 | 株式会社 加ト吉 | Method for manufacturing tray-stuffed sashimi |
-
1982
- 1982-07-07 JP JP10366182U patent/JPS599617U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5850715B2 (en) * | 1981-10-13 | 1983-11-11 | 株式会社 加ト吉 | Method for manufacturing tray-stuffed sashimi |
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