JPH01141470U - - Google Patents

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Publication number
JPH01141470U
JPH01141470U JP3928188U JP3928188U JPH01141470U JP H01141470 U JPH01141470 U JP H01141470U JP 3928188 U JP3928188 U JP 3928188U JP 3928188 U JP3928188 U JP 3928188U JP H01141470 U JPH01141470 U JP H01141470U
Authority
JP
Japan
Prior art keywords
circuit
detection circuit
detection
voltage measurement
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3928188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3928188U priority Critical patent/JPH01141470U/ja
Publication of JPH01141470U publication Critical patent/JPH01141470U/ja
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す接続図、第
2図はこの考案の動作を説明するための波形図、
第3図は従来の技術を説明するための接続図、第
4図は従来の回路の欠点を説明するための波形図
である。 1:入力端子、2:検波回路、5:演算増幅器
、12:直流阻止用コンデンサ、13:積分器。
Fig. 1 is a connection diagram showing an embodiment of this invention, Fig. 2 is a waveform diagram for explaining the operation of this invention,
FIG. 3 is a connection diagram for explaining the conventional technique, and FIG. 4 is a waveform diagram for explaining the drawbacks of the conventional circuit. 1: Input terminal, 2: Detection circuit, 5: Operational amplifier, 12: DC blocking capacitor, 13: Integrator.

Claims (1)

【実用新案登録請求の範囲】 A 検波回路と、この検波回路の検波出力信号を
自乗平均し、交流入力電圧信号の実効値に対応す
る直流電圧を出力する交流電圧測定回路において
、 B 上記検波回路を構成する演算増幅器の出力端
子と整流回路との間に接続した直流阻止用コンデ
ンサと、 C この直流阻止用コンデンサに蓄積される直流
分を積分し、その積分出力を上記演算増幅器の入
力端子に負帰還する積分器と、 を備えて成る交流電圧測定回路。
[Scope of Claim for Utility Model Registration] A. A detection circuit and an AC voltage measurement circuit that takes the root mean square of the detection output signal of the detection circuit and outputs a DC voltage corresponding to the effective value of the AC input voltage signal, B. The above-mentioned detection circuit. A DC blocking capacitor connected between the output terminal of the operational amplifier and the rectifying circuit constituting C. An AC voltage measurement circuit comprising an integrator that provides negative feedback, and
JP3928188U 1988-03-24 1988-03-24 Pending JPH01141470U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3928188U JPH01141470U (en) 1988-03-24 1988-03-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3928188U JPH01141470U (en) 1988-03-24 1988-03-24

Publications (1)

Publication Number Publication Date
JPH01141470U true JPH01141470U (en) 1989-09-28

Family

ID=31265791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3928188U Pending JPH01141470U (en) 1988-03-24 1988-03-24

Country Status (1)

Country Link
JP (1) JPH01141470U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396650A (en) * 1977-02-02 1978-08-24 Nec Corp Automatic adjustment circuit for offset voltage
JPS6230473U (en) * 1985-08-05 1987-02-24

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396650A (en) * 1977-02-02 1978-08-24 Nec Corp Automatic adjustment circuit for offset voltage
JPS6230473U (en) * 1985-08-05 1987-02-24

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