JPS637820U - - Google Patents

Info

Publication number
JPS637820U
JPS637820U JP1986100107U JP10010786U JPS637820U JP S637820 U JPS637820 U JP S637820U JP 1986100107 U JP1986100107 U JP 1986100107U JP 10010786 U JP10010786 U JP 10010786U JP S637820 U JPS637820 U JP S637820U
Authority
JP
Japan
Prior art keywords
circuit
pulse
output
comparator circuit
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986100107U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986100107U priority Critical patent/JPS637820U/ja
Publication of JPS637820U publication Critical patent/JPS637820U/ja
Pending legal-status Critical Current

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Landscapes

  • Pulse Circuits (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この考案のパルス周波数変調回路の
一実施例を示す回路図、第2図は、第1図に示し
た回路各部の信号波形図、第3図は、従来の二重
積分型AD変換器の一例を示す回路図である。 11……パルス周波数変調回路、12……積分
回路、13……比較回路、14……リセツト回路
Fig. 1 is a circuit diagram showing one embodiment of the pulse frequency modulation circuit of this invention, Fig. 2 is a signal waveform diagram of each part of the circuit shown in Fig. 1, and Fig. 3 is a conventional double integral type It is a circuit diagram showing an example of an AD converter. 11...Pulse frequency modulation circuit, 12...Integrator circuit, 13...Comparison circuit, 14...Reset circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力アナログ信号を時間積分する積分回路と、
この積分回路の出力があらかじめ設定された所定
の比較基準を上回つたときに周波数変調パルスを
出力する比較回路と、この比較回路の出力パルス
が一定パルス幅に達したことを検出して動作し、
前記積分回路を初期値出力状態にリセツトするリ
セツト回路とからなるパルス周波数変調回路。
an integrating circuit that time-integrates an input analog signal;
There is a comparator circuit that outputs a frequency modulated pulse when the output of this integrator circuit exceeds a preset comparison standard, and a comparator circuit that operates by detecting that the output pulse of this comparator circuit has reached a certain pulse width. ,
A pulse frequency modulation circuit comprising a reset circuit for resetting the integrating circuit to an initial value output state.
JP1986100107U 1986-06-30 1986-06-30 Pending JPS637820U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986100107U JPS637820U (en) 1986-06-30 1986-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986100107U JPS637820U (en) 1986-06-30 1986-06-30

Publications (1)

Publication Number Publication Date
JPS637820U true JPS637820U (en) 1988-01-19

Family

ID=30969614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986100107U Pending JPS637820U (en) 1986-06-30 1986-06-30

Country Status (1)

Country Link
JP (1) JPS637820U (en)

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