JPS62162671U - - Google Patents

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Publication number
JPS62162671U
JPS62162671U JP5028686U JP5028686U JPS62162671U JP S62162671 U JPS62162671 U JP S62162671U JP 5028686 U JP5028686 U JP 5028686U JP 5028686 U JP5028686 U JP 5028686U JP S62162671 U JPS62162671 U JP S62162671U
Authority
JP
Japan
Prior art keywords
circuit
output
absolute value
reference voltage
constant amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5028686U
Other languages
Japanese (ja)
Other versions
JPH0521026Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5028686U priority Critical patent/JPH0521026Y2/ja
Publication of JPS62162671U publication Critical patent/JPS62162671U/ja
Application granted granted Critical
Publication of JPH0521026Y2 publication Critical patent/JPH0521026Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例を示すブロツク図、第
２図は同じくその動作特性を示すタイミングチヤ
ート、第３図は従来例のブロツク図である。 ２０……定振幅回路、２１……積分回路、２２
……直流分除去回路、２３……基準電圧加算回路
、２４……絶対値回路、２５……基準電圧減算回
路、２６……平滑回路。 FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing its operating characteristics, and FIG. 3 is a block diagram of a conventional example. 20... Constant amplitude circuit, 21... Integrating circuit, 22
... DC component removal circuit, 23 ... Reference voltage addition circuit, 24 ... Absolute value circuit, 25 ... Reference voltage subtraction circuit, 26 ... Smoothing circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力振動波を一定振幅の矩形波に整形する定振
幅回路と、この出力を積分する積分回路と、積分
出力から直流分を除去するとともに所定の基準電
圧を加算する回路と、この加算出力の前記基準電
圧からの偏差の絶対値を求める絶対値回路と、こ
の絶対値出力に対応した出力を平均化する平滑回
路とを備えたことを特徴とする周期・電圧変換回
路。 a constant amplitude circuit that shapes an input vibration wave into a rectangular wave of constant amplitude; an integrating circuit that integrates this output; a circuit that removes a DC component from the integrated output and adds a predetermined reference voltage; A period/voltage conversion circuit comprising: an absolute value circuit that determines the absolute value of a deviation from a reference voltage; and a smoothing circuit that averages an output corresponding to this absolute value output.
JP5028686U 1986-04-03 1986-04-03 Expired - Lifetime JPH0521026Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5028686U JPH0521026Y2 (en) 1986-04-03 1986-04-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5028686U JPH0521026Y2 (en) 1986-04-03 1986-04-03

Publications (2)

Publication Number Publication Date
JPS62162671U true JPS62162671U (en) 1987-10-16
JPH0521026Y2 JPH0521026Y2 (en) 1993-05-31

Family

ID=30873509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5028686U Expired - Lifetime JPH0521026Y2 (en) 1986-04-03 1986-04-03

Country Status (1)

Country Link
JP (1) JPH0521026Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02230821A (en) * 1989-03-03 1990-09-13 Hitachi Ltd Clock generator and information processing system using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02230821A (en) * 1989-03-03 1990-09-13 Hitachi Ltd Clock generator and information processing system using the same

Also Published As

Publication number Publication date
JPH0521026Y2 (en) 1993-05-31

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