JPS6164743U - - Google Patents
Info
- Publication number
- JPS6164743U JPS6164743U JP1984150011U JP15001184U JPS6164743U JP S6164743 U JPS6164743 U JP S6164743U JP 1984150011 U JP1984150011 U JP 1984150011U JP 15001184 U JP15001184 U JP 15001184U JP S6164743 U JPS6164743 U JP S6164743U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- voltage
- delay time
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010354 integration Effects 0.000 claims 2
- 238000004092 self-diagnosis Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案によるパルス遅延時間モニター
回路の構成を示すブロツク図、第２図は第１図に
示した構成で得られる出力パルスと直流電圧の関
係を示す波形図、第３図は従来のパルス発生装置
の構成を示すブロツク図、第４図は従来のパルス
発生回路にて出力されるパルスと直流電圧の関係
を示す波形図である。
１…パルス発生部、２…比較部、３…Ａ／Ｄコ
ンバータ、４…パルス発生回路、５…サンプルホ
ールド回路、６…積分回路、７…制御回路、８…
電圧比較回路。
Figure 1 is a block diagram showing the configuration of a pulse delay time monitor circuit according to the present invention, Figure 2 is a waveform diagram showing the relationship between the output pulse and DC voltage obtained with the configuration shown in Figure 1, and Figure 3 is a conventional circuit. FIG. 4 is a waveform diagram showing the relationship between the pulses output from the conventional pulse generating circuit and the DC voltage. DESCRIPTION OF SYMBOLS 1...Pulse generation part, 2...Comparison part, 3...A/D converter, 4...Pulse generation circuit, 5...Sample hold circuit, 6...Integrator circuit, 7...Control circuit, 8...
Voltage comparison circuit.
Claims (1)
を制御するパルス発生装置の遅延時間自己診断回
路であつて、アナログ直流電圧を一定時間保持す
るサンプルホールド回路と、演算増幅器を使用し
た積分回路と、該積分回路の鋸歯状波信号を基準
パルスからスタートさせる制御回路と、前記直流
電圧と鋸歯状波信号を比較し一致した時点でパル
ス信号を発生する電圧比較回路とから成るパルス
遅延時間モニター回路。 A delay time self-diagnosis circuit for a pulse generator that controls pulse delay time based on an analog DC voltage value, which includes a sample hold circuit that holds an analog DC voltage for a certain period of time, an integration circuit that uses an operational amplifier, and an integration circuit that uses an operational amplifier. A pulse delay time monitor circuit comprising a control circuit that starts the sawtooth wave signal of the integrating circuit from a reference pulse, and a voltage comparison circuit that compares the DC voltage and the sawtooth wave signal and generates a pulse signal when they match.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984150011U JPS6164743U (en) | 1984-10-03 | 1984-10-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984150011U JPS6164743U (en) | 1984-10-03 | 1984-10-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6164743U true JPS6164743U (en) | 1986-05-02 |
Family
ID=30708168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984150011U Pending JPS6164743U (en) | 1984-10-03 | 1984-10-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6164743U (en) |
-
1984
- 1984-10-03 JP JP1984150011U patent/JPS6164743U/ja active Pending