JPH0158177U - - Google Patents
Info
- Publication number
- JPH0158177U JPH0158177U JP15315687U JP15315687U JPH0158177U JP H0158177 U JPH0158177 U JP H0158177U JP 15315687 U JP15315687 U JP 15315687U JP 15315687 U JP15315687 U JP 15315687U JP H0158177 U JPH0158177 U JP H0158177U
- Authority
- JP
- Japan
- Prior art keywords
- input
- frequency
- counter
- ary counter
- reset pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000001960 triggered effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の一実施例によるＦ―Ｖコン
バータの構成図、第２図はタイミングチヤート、
第３図はＦ―Ｖ変換特性図、第４図は従来のＦ―
Ｖコンバータの構成図である。
２…積分回路、３…ｎ進カウンタ、４…リセツ
トパルス発生器、ａ…入力パルス、ｂ…リセツト
パルス、ｃ…出力パルス。なお、図中の同一符号
は同一または相当部分を示す。
Figure 1 is a configuration diagram of an F-V converter according to an embodiment of this invention, Figure 2 is a timing chart,
Figure 3 is an F-V conversion characteristic diagram, and Figure 4 is a conventional F-V conversion characteristic diagram.
It is a block diagram of a V converter. 2...Integrator circuit, 3...N-ary counter, 4...Reset pulse generator, a...Input pulse, b...Reset pulse, c...Output pulse. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
トリガされるｎ進カウンタと、このｎ進カウンタ
による入力パルスのカウントを制御するためのリ
セツトパルスをｎ進カウンタに入力するリセツト
パルス発生器と、上記ｎ進カウンタからの出力パ
ルスを積分して出力する積分回路とを具備し、入
力周波数の変化に対応させて積分回路の出力電圧
を可変制御するように構成したことを特徴とする
周波数一電圧変換回路。 an n-ary counter that is triggered by applying an input pulse with a variable frequency; a reset pulse generator that inputs a reset pulse to the n-ary counter for controlling the counting of input pulses by the n-ary counter; What is claimed is: 1. A frequency-to-voltage conversion circuit comprising: an integrating circuit that integrates and outputs output pulses from a counter; and configured to variably control the output voltage of the integrating circuit in response to changes in input frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15315687U JPH0158177U (en) | 1987-10-05 | 1987-10-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15315687U JPH0158177U (en) | 1987-10-05 | 1987-10-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0158177U true JPH0158177U (en) | 1989-04-11 |
Family
ID=31428740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15315687U Pending JPH0158177U (en) | 1987-10-05 | 1987-10-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0158177U (en) |
-
1987
- 1987-10-05 JP JP15315687U patent/JPH0158177U/ja active Pending