JPS62161596U - - Google Patents
Info
- Publication number
- JPS62161596U JPS62161596U JP1986047855U JP4785586U JPS62161596U JP S62161596 U JPS62161596 U JP S62161596U JP 1986047855 U JP1986047855 U JP 1986047855U JP 4785586 U JP4785586 U JP 4785586U JP S62161596 U JPS62161596 U JP S62161596U
- Authority
- JP
- Japan
- Prior art keywords
- input
- capacitor
- input terminal
- terminal
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案を示す回路図、第２図は第１図
の各部波形を示すタイミングチヤート、第３図は
従来のモータの速度制御回路を示す回路図、第４
図は第３図の各部波形を示すタイミングチヤート
である。
２…演算増幅器、３…入力抵抗、５…コンデン
サ、６…フイードバツク抵抗、９，１０…ダイオ
ード。
Fig. 1 is a circuit diagram showing the present invention, Fig. 2 is a timing chart showing waveforms of each part of Fig. 1, Fig. 3 is a circuit diagram showing a conventional motor speed control circuit, and Fig. 4 is a circuit diagram showing the waveform of each part of Fig. 1.
The figure is a timing chart showing waveforms of various parts in FIG. 3. 2...Operation amplifier, 3...Input resistance, 5...Capacitor, 6...Feedback resistance, 9, 10...Diode.
Claims (1)
抗を介して比較電圧が入力される他方の入力端子
、及び前記両入力によつてモータの速度制御用の
制御電圧が出力される出力端子を有する演算増幅
器と、前記他方の入力端子及び出力端子間に直列
接続されたコンデンサ及びフイードバツク抵抗と
、前記コンデンサに並列接続されると共に異極同
士が接続された第１及び第２のダイオードより成
ることを特徴とするモータの速度制御回路。 It has one input terminal to which a reference voltage is input, the other input terminal to which a comparison voltage is input via an input resistor, and an output terminal to which a control voltage for controlling the speed of the motor is outputted from both inputs. An operational amplifier, a capacitor and a feedback resistor connected in series between the other input terminal and the output terminal, and first and second diodes connected in parallel to the capacitor and having different polarities connected to each other. Features a motor speed control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986047855U JPS62161596U (en) | 1986-03-31 | 1986-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986047855U JPS62161596U (en) | 1986-03-31 | 1986-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62161596U true JPS62161596U (en) | 1987-10-14 |
Family
ID=30868853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986047855U Pending JPS62161596U (en) | 1986-03-31 | 1986-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62161596U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6333919A (en) * | 1986-07-29 | 1988-02-13 | Sony Corp | Sin2 waveform shaping circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57145590A (en) * | 1981-03-05 | 1982-09-08 | Japanese National Railways<Jnr> | Load control device |
-
1986
- 1986-03-31 JP JP1986047855U patent/JPS62161596U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57145590A (en) * | 1981-03-05 | 1982-09-08 | Japanese National Railways<Jnr> | Load control device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6333919A (en) * | 1986-07-29 | 1988-02-13 | Sony Corp | Sin2 waveform shaping circuit |