JPH0291487U - - Google Patents
Info
- Publication number
- JPH0291487U JPH0291487U JP16981188U JP16981188U JPH0291487U JP H0291487 U JPH0291487 U JP H0291487U JP 16981188 U JP16981188 U JP 16981188U JP 16981188 U JP16981188 U JP 16981188U JP H0291487 U JPH0291487 U JP H0291487U
- Authority
- JP
- Japan
- Prior art keywords
- regulator circuit
- switching regulator
- pulse generation
- output pulses
- generation circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Dc-Dc Converters (AREA)
Description
第１図は本考案の一実施例を示すスイツチング
レギユレータ回路を示す図、第２図、第３図は実
施例の動作を示すタイミングチヤート、第４図は
従来のスイツチングレギユレータ回路の構成を示
す図である。
１：入力電圧、２：コイル、３：ダイオード、
４：コンデンサ、５：出力トランジスタ、６：ラ
ツチ回路、７：発振回路、８：差動増幅器、９：
基準電圧源、１０：ブリーダ抵抗、１１：マルチ
プレクサ、１２ａ〜１２ｎ：パルス発生回路、１
３ａ〜１３ｎ―１：ラツチ回路。
Fig. 1 is a diagram showing a switching regulator circuit showing an embodiment of the present invention, Figs. 2 and 3 are timing charts showing the operation of the embodiment, and Fig. 4 is a diagram showing a conventional switching regulator circuit. FIG. 3 is a diagram showing the configuration of a circuit. 1: Input voltage, 2: Coil, 3: Diode,
4: Capacitor, 5: Output transistor, 6: Latch circuit, 7: Oscillator circuit, 8: Differential amplifier, 9:
Reference voltage source, 10: Bleeder resistor, 11: Multiplexer, 12a to 12n: Pulse generation circuit, 1
3a to 13n-1: Latch circuit.
Claims (1)
路において、デユーテイ比の異なる複数のパルス
発生回路からの出力パルスを順次切替える手段を
設けて、負荷または入力電圧に応じて前記デユー
テイ比の異なる複数のパルス発生回路からの出力
パルスを順次切替えるように構成したことを特徴
とするスイツチングレギユレータ回路。 In the switching regulator circuit for off-time control, means is provided for sequentially switching output pulses from a plurality of pulse generation circuits having different duty ratios, and the plurality of pulse generation circuits having different duty ratios are controlled according to the load or input voltage. 1. A switching regulator circuit configured to sequentially switch output pulses from a switching regulator circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16981188U JPH0291487U (en) | 1988-12-28 | 1988-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16981188U JPH0291487U (en) | 1988-12-28 | 1988-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0291487U true JPH0291487U (en) | 1990-07-19 |
Family
ID=31460202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16981188U Pending JPH0291487U (en) | 1988-12-28 | 1988-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0291487U (en) |
-
1988
- 1988-12-28 JP JP16981188U patent/JPH0291487U/ja active Pending