JPS59169116U - Noise removal circuit - Google Patents
Noise removal circuitInfo
- Publication number
- JPS59169116U JPS59169116U JP6302683U JP6302683U JPS59169116U JP S59169116 U JPS59169116 U JP S59169116U JP 6302683 U JP6302683 U JP 6302683U JP 6302683 U JP6302683 U JP 6302683U JP S59169116 U JPS59169116 U JP S59169116U
- Authority
- JP
- Japan
- Prior art keywords
- noise removal
- removal circuit
- audio signal
- detection means
- delay device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は遅延装置を使用した一例を示すブロック図、第
２図は本考案の一実施例を示すブロック図、第３図は本
考案の一実施例を第１図に示した遅延装置に適用した場
合のブロック図、第４図は本考案の一実施例の具体的回
路を示す回路図である。
４・・・フラット増幅器、６および８・・・ローパスフ
ィルタ、７・・・ＢＢＤ、 ｌ ｌ・・・遅延信号出力
端子、１２・・・雑音除去回路、１２−１・・・増幅器
、１２−２・・・倍電圧整流回路、１２−８・・・制御
回路、１２−１・・・アナログスイッチ。Fig. 1 is a block diagram showing an example of using a delay device, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a block diagram showing an embodiment of the present invention using the delay device shown in Fig. 1. FIG. 4 is a block diagram showing a specific circuit of an embodiment of the present invention. 4... Flat amplifier, 6 and 8... Low pass filter, 7... BBD, l l... Delayed signal output terminal, 12... Noise removal circuit, 12-1... Amplifier, 12- 2... Voltage doubler rectifier circuit, 12-8... Control circuit, 12-1... Analog switch.
Claims (1)
を備えた遅延装置の雑音を除去する雑音除去回路であっ
て、音声信号の有無を検出する検出手段と、遅延装置の
出力ラインに挿入されたアナログスイッチと、音声信号
の有ることを検出した前記検出手段の出力により前記ア
ナログスイッチをオン状態に制御し、かつ音声信号の無
いことを検出した前記検出手段の出力により前記アナロ
グスイッチをオフ状態に制御する制御手段とを備えてな
ることを特徴とする雑音除去回路。A noise removal circuit that removes noise from a delay device that is equipped with an electronic delay device that delays and outputs a supplied audio signal, the circuit comprising: a detection means that detects the presence or absence of an audio signal; and a detection means that is inserted into the output line of the delay device. The analog switch is turned on by the output of the detection means that detects the presence of the audio signal, and the analog switch is turned off by the output of the detection means that detects the absence of the audio signal. 1. A noise removal circuit comprising: control means for controlling the state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6302683U JPS59169116U (en) | 1983-04-28 | 1983-04-28 | Noise removal circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6302683U JPS59169116U (en) | 1983-04-28 | 1983-04-28 | Noise removal circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59169116U true JPS59169116U (en) | 1984-11-12 |
Family
ID=30193215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6302683U Pending JPS59169116U (en) | 1983-04-28 | 1983-04-28 | Noise removal circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59169116U (en) |
-
1983
- 1983-04-28 JP JP6302683U patent/JPS59169116U/en active Pending
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