JPS5971438U - tape deck - Google Patents
tape deckInfo
- Publication number
- JPS5971438U JPS5971438U JP16305982U JP16305982U JPS5971438U JP S5971438 U JPS5971438 U JP S5971438U JP 16305982 U JP16305982 U JP 16305982U JP 16305982 U JP16305982 U JP 16305982U JP S5971438 U JPS5971438 U JP S5971438U
- Authority
- JP
- Japan
- Prior art keywords
- reset signal
- tape deck
- turned
- main power
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のテープデツキのリセット信号発生回路の
回路図、第２図は本考案の一実施例よりなるテープデツ
キのリセット信号発生回路の回路図、第３図ａ、 ｂ
は第２図の回路の各部の電圧波形図、第４図は本考案の
他の実施例よりなるリセット信号発生回路の回路図、お
よび第５図は第４図の回路の各部の電圧波形図である。
１．１′・・・・・・制御回路、２．２′・・・・・・
リセット信号発生回路、３・・・・・・定電圧回路、４
・・・・・・制御回路保持電源。Fig. 1 is a circuit diagram of a conventional tape deck reset signal generation circuit, Fig. 2 is a circuit diagram of a tape deck reset signal generation circuit according to an embodiment of the present invention, and Figs. 3a and b.
2 is a voltage waveform diagram of each part of the circuit of FIG. 2, FIG. 4 is a circuit diagram of a reset signal generation circuit according to another embodiment of the present invention, and FIG. 5 is a voltage waveform diagram of various parts of the circuit of FIG. 4. It is. 1.1'...Control circuit, 2.2'...
Reset signal generation circuit, 3... Constant voltage circuit, 4
...Control circuit holding power supply.
Claims (1)
、主電源投入時は制御回路用電源が安定するまでのある
一定時間、リセット信号を発生し、主電源が切られた時
にはその瞬間単一パルスのリセット信号を発生するリセ
ット信号発生回路とを有するテープデツキ。The control circuit power is maintained for a certain period of time even after the main power is turned off, and when the main power is turned on, a reset signal is generated for a certain period of time until the control circuit power is stabilized, and when the main power is turned off, a reset signal is generated at that moment. A tape deck having a reset signal generation circuit that generates a single pulse reset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16305982U JPS5971438U (en) | 1982-10-29 | 1982-10-29 | tape deck |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16305982U JPS5971438U (en) | 1982-10-29 | 1982-10-29 | tape deck |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5971438U true JPS5971438U (en) | 1984-05-15 |
Family
ID=30357889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16305982U Pending JPS5971438U (en) | 1982-10-29 | 1982-10-29 | tape deck |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5971438U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5766510A (en) * | 1980-10-13 | 1982-04-22 | Toshiba Corp | Power source circuit of electronic control type tape recorder |
-
1982
- 1982-10-29 JP JP16305982U patent/JPS5971438U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5766510A (en) * | 1980-10-13 | 1982-04-22 | Toshiba Corp | Power source circuit of electronic control type tape recorder |
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