JPH0244474U - - Google Patents

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Publication number
JPH0244474U
JPH0244474U JP12392088U JP12392088U JPH0244474U JP H0244474 U JPH0244474 U JP H0244474U JP 12392088 U JP12392088 U JP 12392088U JP 12392088 U JP12392088 U JP 12392088U JP H0244474 U JPH0244474 U JP H0244474U
Authority
JP
Japan
Prior art keywords
input terminal
synchronization signal
circuit
field discrimination
clock input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12392088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12392088U priority Critical patent/JPH0244474U/ja
Publication of JPH0244474U publication Critical patent/JPH0244474U/ja
Pending legal-status Critical Current

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  • Synchronizing For Television (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す回路図。第2
図は第1図の動作を示すタイミングチヤート図。 2……外部同期信号発生器、4……FF、8…
…遅延回路、10……パルス幅延長回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. Second
The figure is a timing chart showing the operation of FIG. 1. 2...External synchronization signal generator, 4...FF, 8...
...Delay circuit, 10...Pulse width extension circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部からの垂直同期信号と水平同期信号とをD
入力端子およびクロツク入力端子に供給されるF
Fと、このFFの出力端子がカメラ部の内部同期
信号発生回路に接続されたフイールド判別回路に
おいて、前記FFのクロツク入力端子に遅延回路
を接続するとともにD入力端子にパルス幅を延長
するパルス幅延長回路を接続したことを特徴とす
るフイールド判別回路。
The external vertical synchronization signal and horizontal synchronization signal are
F supplied to input terminal and clock input terminal
F and a field discrimination circuit in which the output terminal of this FF is connected to the internal synchronization signal generation circuit of the camera section, a delay circuit is connected to the clock input terminal of the FF, and the pulse width is extended to the D input terminal. A field discrimination circuit characterized by connecting an extension circuit.
JP12392088U 1988-09-20 1988-09-20 Pending JPH0244474U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12392088U JPH0244474U (en) 1988-09-20 1988-09-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12392088U JPH0244474U (en) 1988-09-20 1988-09-20

Publications (1)

Publication Number Publication Date
JPH0244474U true JPH0244474U (en) 1990-03-27

Family

ID=31373208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12392088U Pending JPH0244474U (en) 1988-09-20 1988-09-20

Country Status (1)

Country Link
JP (1) JPH0244474U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62140559A (en) * 1985-12-13 1987-06-24 Nec Home Electronics Ltd Field discrimination circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62140559A (en) * 1985-12-13 1987-06-24 Nec Home Electronics Ltd Field discrimination circuit

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