JPS6392422U - - Google Patents
Info
- Publication number
- JPS6392422U JPS6392422U JP18756086U JP18756086U JPS6392422U JP S6392422 U JPS6392422 U JP S6392422U JP 18756086 U JP18756086 U JP 18756086U JP 18756086 U JP18756086 U JP 18756086U JP S6392422 U JPS6392422 U JP S6392422U
- Authority
- JP
- Japan
- Prior art keywords
- signal delay
- clock
- generation circuit
- delay element
- clock generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 230000001105 regulatory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Networks Using Active Elements (AREA)
Description
第１図は本考案の信号遅延デバイスの構成図、
第２図は一実施例のＦＦ回路の回路図、第３図は
一実施例の信号遅延デバイス信号波形図、第４図
は従来の信号遅延デバイス構成図である。
図において、１−１〜１−ｎはトランジスタ（
ＦＥＴ）、２−１〜２−ｎはコンデンサ、３は信
号遅延素子、４はクロツク発生回路、５はパルス
発生回路、６はフリツプフロツプ回路（ＦＦ回路
）、７……リセツト機能を示している。
FIG. 1 is a configuration diagram of the signal delay device of the present invention.
FIG. 2 is a circuit diagram of an FF circuit of one embodiment, FIG. 3 is a signal waveform diagram of a signal delay device of one embodiment, and FIG. 4 is a configuration diagram of a conventional signal delay device. In the figure, 1-1 to 1-n are transistors (
2-1 to 2-n are capacitors, 3 is a signal delay element, 4 is a clock generation circuit, 5 is a pulse generation circuit, 6 is a flip-flop circuit (FF circuit), and 7... is a reset function.
Claims (1)
を接続し、前記接続個所とアース間に設けられた
コンデンサ１−１〜１−ｎとから成る信号遅延素
子３と、該信号遅延素子３を駆動するクロツクを
発生するクロツク発生回路４とを備えた信号遅延
デバイスにおいて、 前記クロツク発生回路４に前記クロツクの発生
タイミングを規制するリセツト機能７を設けたこ
とを特徴とする信号遅延デバイス。[Claims for Utility Model Registration] Plural transistors 1-1 to 1-n in series
A signal delay element 3 comprising capacitors 1-1 to 1-n connected to each other and provided between the connection point and ground, and a clock generation circuit 4 for generating a clock for driving the signal delay element 3. 1. A signal delay device characterized in that the clock generation circuit 4 is provided with a reset function 7 for regulating the timing of generation of the clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18756086U JPS6392422U (en) | 1986-12-04 | 1986-12-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18756086U JPS6392422U (en) | 1986-12-04 | 1986-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6392422U true JPS6392422U (en) | 1988-06-15 |
Family
ID=31138134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18756086U Pending JPS6392422U (en) | 1986-12-04 | 1986-12-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6392422U (en) |
-
1986
- 1986-12-04 JP JP18756086U patent/JPS6392422U/ja active Pending
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