JPH0270525U - - Google Patents

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Publication number
JPH0270525U
JPH0270525U JP14918588U JP14918588U JPH0270525U JP H0270525 U JPH0270525 U JP H0270525U JP 14918588 U JP14918588 U JP 14918588U JP 14918588 U JP14918588 U JP 14918588U JP H0270525 U JPH0270525 U JP H0270525U
Authority
JP
Japan
Prior art keywords
output
monostable multivibrator
input
gate
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14918588U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14918588U priority Critical patent/JPH0270525U/ja
Publication of JPH0270525U publication Critical patent/JPH0270525U/ja
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の回路のブロツク図、第2図は
第1図の各部の波形を示す図である。 C,C……コンデンサ、G1〜G3……イ
ンバーター、G4……NORゲート、M1……モ
ノステーブルマルチバイブレーター、N1……積
分回路、R,R……抵抗、VCC……電源電
圧。
FIG. 1 is a block diagram of the circuit of the present invention, and FIG. 2 is a diagram showing waveforms at various parts of FIG. 1. C 1 , C 2 ... Capacitor, G1 to G3 ... Inverter, G4 ... NOR gate, M1 ... Monostable multivibrator, N1 ... Integrating circuit, R 1 , R 2 ... Resistor, VCC ... Power supply voltage .

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 信号線より入力された入力信号により駆動され
るモノステーブルマルチバイブレーターと、前記
入力信号から前記モノステーブルマルチバイブレ
ーター出力までの遅延を補正する遅延回路および
前記モノステーブルマルチバイブレーター出力と
前記遅延回路出力を入力とするNORゲートとか
ら構成されることを特徴とするパルス性ノイズ除
去回路。
A monostable multivibrator driven by an input signal input from a signal line, a delay circuit that corrects a delay from the input signal to the output of the monostable multivibrator, and an output of the monostable multivibrator and an output of the delay circuit are input. 1. A pulse noise removal circuit comprising: a NOR gate; and a NOR gate.
JP14918588U 1988-11-15 1988-11-15 Pending JPH0270525U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14918588U JPH0270525U (en) 1988-11-15 1988-11-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14918588U JPH0270525U (en) 1988-11-15 1988-11-15

Publications (1)

Publication Number Publication Date
JPH0270525U true JPH0270525U (en) 1990-05-29

Family

ID=31421185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14918588U Pending JPH0270525U (en) 1988-11-15 1988-11-15

Country Status (1)

Country Link
JP (1) JPH0270525U (en)

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