JPH01107224U - - Google Patents
Info
- Publication number
- JPH01107224U JPH01107224U JP142588U JP142588U JPH01107224U JP H01107224 U JPH01107224 U JP H01107224U JP 142588 U JP142588 U JP 142588U JP 142588 U JP142588 U JP 142588U JP H01107224 U JPH01107224 U JP H01107224U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- clock pulse
- output
- input terminal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
Description
第１図は本考案による信号発生回路の一実施例
を示す回路図、第２図は第１図の信号発生回路の
動作タイミングを示すタイムチヤートである。第
３図は従来の信号発生回路の一例を示す回路図、
第４図は第３図の信号発生回路の動作タイミング
を示すタイムチヤートである。
１０……信号発生回路；１１……カウンタ；１
２，１３……外部入力端子；１４……外部出力端
子。
FIG. 1 is a circuit diagram showing an embodiment of the signal generating circuit according to the present invention, and FIG. 2 is a time chart showing the operation timing of the signal generating circuit of FIG. FIG. 3 is a circuit diagram showing an example of a conventional signal generation circuit,
FIG. 4 is a time chart showing the operation timing of the signal generating circuit of FIG. 3. 10... Signal generation circuit; 11... Counter; 1
2, 13...External input terminal; 14...External output terminal.
Claims (1)
パルスにより複数の出力端子に対して順次信号を
出力するカウンタを含んでおり、このカウンタの
（ｎ＋１）番目の出力端子が、該カウンタのカウ
ント制御入力端子に接続されていて、リセツト信
号が該カウンタに入力された後、ｎ番目のクロツ
クパルスの立上りのタイミングでスタート信号を
出力するようにしたことを特徴とする、信号発生
回路。 It includes a counter that sequentially outputs signals to a plurality of output terminals in response to a clock pulse input to a clock pulse input terminal, and the (n+1)th output terminal of this counter is connected to the count control input terminal of the counter. 1. A signal generating circuit, characterized in that, after a reset signal is input to said counter, a start signal is output at the timing of a rising edge of an n-th clock pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP142588U JPH0432819Y2 (en) | 1988-01-09 | 1988-01-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP142588U JPH0432819Y2 (en) | 1988-01-09 | 1988-01-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01107224U true JPH01107224U (en) | 1989-07-19 |
| JPH0432819Y2 JPH0432819Y2 (en) | 1992-08-06 |
Family
ID=31201297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP142588U Expired JPH0432819Y2 (en) | 1988-01-09 | 1988-01-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0432819Y2 (en) |
-
1988
- 1988-01-09 JP JP142588U patent/JPH0432819Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0432819Y2 (en) | 1992-08-06 |
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