JPH0191334U - - Google Patents

Info

Publication number
JPH0191334U
JPH0191334U JP18743287U JP18743287U JPH0191334U JP H0191334 U JPH0191334 U JP H0191334U JP 18743287 U JP18743287 U JP 18743287U JP 18743287 U JP18743287 U JP 18743287U JP H0191334 U JPH0191334 U JP H0191334U
Authority
JP
Japan
Prior art keywords
carry
counter
set value
presettable
presettable counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18743287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18743287U priority Critical patent/JPH0191334U/ja
Publication of JPH0191334U publication Critical patent/JPH0191334U/ja
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案による実施例の構成図、第2
図は第1図の波形図である。 1……プリセツタブルカウンタ(カウンタ)、
2……リングカウンタ、2A〜2E……出力、1
1……データ入力、12……クロツク入力、13
……ロード入力、21……クロツク入力、22…
…シリアル入力、23……反転器。
Figure 1 is a configuration diagram of an embodiment according to this invention, Figure 2
The figure is a waveform diagram of FIG. 1. 1... Presettable counter (counter),
2...Ring counter, 2A~2E...Output, 1
1...Data input, 12...Clock input, 13
...Load input, 21...Clock input, 22...
...Serial input, 23...Inverter.

Claims (1)

【実用新案登録請求の範囲】 プリセツタブルカウンタに設定値をセツトし、 前記プリセツタブルカウンタがクロツクを前記
設定値だけカウントしてキヤリーCを出すと、前
記キヤリーCを前記プリセツタブルカウンタのロ
ード入力に接続するとともに、前記キヤリーCを
n段のリングカウンタに加え、 前記リングカウンタから前記キヤリーCの周期
を位相差とする2nのタイミングを取り出すこと
を特徴とするタイミング発生回路。
[Claims for Utility Model Registration] A set value is set in a presettable counter, and when the presettable counter counts clocks by the set value and outputs a carry C, the carry C is transferred to the presettable counter. A timing generation circuit characterized in that it is connected to a load input, adds the carry C to an n-stage ring counter, and extracts 2n timings having a phase difference equal to the period of the carry C from the ring counter.
JP18743287U 1987-12-09 1987-12-09 Pending JPH0191334U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18743287U JPH0191334U (en) 1987-12-09 1987-12-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18743287U JPH0191334U (en) 1987-12-09 1987-12-09

Publications (1)

Publication Number Publication Date
JPH0191334U true JPH0191334U (en) 1989-06-15

Family

ID=31478587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18743287U Pending JPH0191334U (en) 1987-12-09 1987-12-09

Country Status (1)

Country Link
JP (1) JPH0191334U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5733727A (en) * 1980-08-08 1982-02-23 Yamatake Honeywell Co Ltd Sequential control of combustion

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5733727A (en) * 1980-08-08 1982-02-23 Yamatake Honeywell Co Ltd Sequential control of combustion

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