JPS61183000U

JPS61183000U -

Info

Publication number: JPS61183000U
Application number: JP6315285U
Authority: JP
Priority date: 1985-04-30
Filing date: 1985-04-30
Publication date: 1986-11-14

Description

[Brief explanation of drawings]

第１図は本考案の実施例によるシフトレジスタ
回路の要部を示す回路図、第２図は第１図の回路
のタイミングチヤートを示す図、第３図は従来例
によるシフトレジスタ回路の一例を示す図、第４
図は同じく他の例の要部を示す回路図、第５図は
第４図の回路で正常なシフト動作を行なう場合の
タイミングチヤートを示す図、第６図は同じく不
安定動作を起こす場合のタイミングチヤートを示
す図である。１１，１３，１６，２１……ライン、１２……
データ入力ライン、１４，２０……オア回路、Ｄ
_１〜Ｄ_ｎ，ＤＫ_−１，ＤＫ……Ｄ型フリツプフロ
ツプ、ＣＰ_１……第１のクロツクパルス、ＣＰ_２……第２のクロツクパルス、ＣＰ_３……第３のク
ロツクパルス、ＣＰ_４……第４のクロツクパルス
。 FIG. 1 is a circuit diagram showing the main parts of a shift register circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a timing chart of the circuit of FIG. 1, and FIG. 3 is an example of a conventional shift register circuit. Figure shown, 4th
Figure 5 is a circuit diagram showing the main parts of another example, Figure 5 is a timing chart when normal shift operation is performed using the circuit in Figure 4, and Figure 6 is a diagram showing the timing chart when unstable operation occurs. FIG. 3 is a diagram showing a timing chart. 11, 13, 16, 21... line, 12...
Data input line, 14, 20...OR circuit, D
₁ to D _n , DK _-1 , DK...D-type flip-flop, _CP1 ...first clock pulse, _CP2 ... second clock pulse, CP ₃ ... third clock pulse, CP ₄ ... fourth clock pulse.

Claims

[Scope of utility model registration request]

A first clock that shifts data by a first clock.
a second register that receives the output of the first register as input data and shifts the data using a second clock; and a clock generation circuit that inputs the first clock and outputs the second clock. 1. A shift register circuit comprising: a delay means for delaying a first clock by a delay time equivalent to a delay time occurring in the clock generation circuit.