JPH02143844U - - Google Patents

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Publication number
JPH02143844U
JPH02143844U JP5255789U JP5255789U JPH02143844U JP H02143844 U JPH02143844 U JP H02143844U JP 5255789 U JP5255789 U JP 5255789U JP 5255789 U JP5255789 U JP 5255789U JP H02143844 U JPH02143844 U JP H02143844U
Authority
JP
Japan
Prior art keywords
carry signal
counter
holding circuit
signal holding
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5255789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5255789U priority Critical patent/JPH02143844U/ja
Publication of JPH02143844U publication Critical patent/JPH02143844U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はこの考案に係るカウンタの
キヤリー信号保持回路の実施例を示し、第1図は
回路図、第2図はカウンタの出力QA,QB,Q
C,QDの全出力信号とキヤリー信号及びDタイ
プフリツプフロツプによるラツチのタイミングを
示すタイムチヤートである。第3図及び第4図は
従来の実施例を示し、第3図は回路図、第4図は
タイムチヤートである。 主な符号の説明、1,2,3,4:同期式4ビ
ツトバイナリカウンタ(カウンタ)、6:スパイ
クパルス、7:Dタイプフリツプフロツプ回路、
8:キヤリー信号。
1 and 2 show an embodiment of a carry signal holding circuit for a counter according to this invention, FIG. 1 is a circuit diagram, and FIG. 2 is a counter output QA, QB, Q.
This is a time chart showing the full output signals of C and QDs, the carry signals, and the timing of latching by a D type flip-flop. 3 and 4 show conventional embodiments, FIG. 3 is a circuit diagram, and FIG. 4 is a time chart. Explanation of main symbols: 1, 2, 3, 4: synchronous 4-bit binary counter (counter), 6: spike pulse, 7: D-type flip-flop circuit,
8: Carry signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] カウンタのキヤリー信号をクロツク同期型のD
タイプフリツプフロツプ回路で保持するように構
成したことを特徴とするカウンタのキヤリー信号
保持回路。
The carry signal of the counter is clock synchronized.
A carry signal holding circuit for a counter, characterized in that the carry signal holding circuit is configured to be held by a type flip-flop circuit.
JP5255789U 1989-05-09 1989-05-09 Pending JPH02143844U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5255789U JPH02143844U (en) 1989-05-09 1989-05-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5255789U JPH02143844U (en) 1989-05-09 1989-05-09

Publications (1)

Publication Number Publication Date
JPH02143844U true JPH02143844U (en) 1990-12-06

Family

ID=31572956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5255789U Pending JPH02143844U (en) 1989-05-09 1989-05-09

Country Status (1)

Country Link
JP (1) JPH02143844U (en)

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