JPH01146640U - - Google Patents
Info
- Publication number
- JPH01146640U JPH01146640U JP4275288U JP4275288U JPH01146640U JP H01146640 U JPH01146640 U JP H01146640U JP 4275288 U JP4275288 U JP 4275288U JP 4275288 U JP4275288 U JP 4275288U JP H01146640 U JPH01146640 U JP H01146640U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- phase comparator
- phase
- latch circuit
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Time-Division Multiplex Systems (AREA)
Description
第１図は本考案の位相比較回路の一実施例を示
す回路図、第２図は本考案に係るタイミングチヤ
ート、第３図は位相比較回路を用いるスタツフ同
期回路のブロツク図、第４図は従来の位相比較回
路、第５図は第４図に示す従来の位相比較回路に
係るタイミングチヤート、第６図はスタツフ同期
を示す図である。
２……非同期クロツク入力端子、３……同期ク
ロツク入力端子、５……位相比較器、９……制御
信号入力端子、１０……リセツト信号入力端子、
１１……出力端子、１３……ラツチ、１４……ナ
ンド（ＮＡＮＤ）ゲート。
Fig. 1 is a circuit diagram showing an embodiment of the phase comparator circuit of the present invention, Fig. 2 is a timing chart according to the present invention, Fig. 3 is a block diagram of a staff synchronization circuit using the phase comparator circuit, and Fig. 4 is a block diagram of a staff synchronization circuit using the phase comparator circuit. 5 is a timing chart relating to the conventional phase comparison circuit shown in FIG. 4, and FIG. 6 is a diagram showing staff synchronization. 2...Asynchronous clock input terminal, 3...Synchronized clock input terminal, 5...Phase comparator, 9...Control signal input terminal, 10...Reset signal input terminal,
11...Output terminal, 13...Latch, 14...NAND gate.
Claims (1)
ツチ回路を備えて構成される位相比較回路におい
て、 同期クロツクに同期した制御信号と前記位相比
較器の出力との論理和により前記ラツチ回路をプ
リセツトする制御手段を具備することを特徴とす
る位相比較回路。[Claims for Utility Model Registration] In a phase comparison circuit used in a staff synchronous circuit and comprising a phase comparator and a latch circuit, a logical sum of a control signal synchronized with a synchronous clock and the output of the phase comparator is provided. A phase comparator circuit comprising: control means for presetting the latch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4275288U JPH01146640U (en) | 1988-03-30 | 1988-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4275288U JPH01146640U (en) | 1988-03-30 | 1988-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01146640U true JPH01146640U (en) | 1989-10-09 |
Family
ID=31269159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4275288U Pending JPH01146640U (en) | 1988-03-30 | 1988-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01146640U (en) |
-
1988
- 1988-03-30 JP JP4275288U patent/JPH01146640U/ja active Pending
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