JPH03113444U - - Google Patents
Info
- Publication number
- JPH03113444U JPH03113444U JP2311890U JP2311890U JPH03113444U JP H03113444 U JPH03113444 U JP H03113444U JP 2311890 U JP2311890 U JP 2311890U JP 2311890 U JP2311890 U JP 2311890U JP H03113444 U JPH03113444 U JP H03113444U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- cpu
- flip
- signal
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 3
Description
第１図は本考案のバスコントロール回路の一実
施例である。図に於いて１はＯＲ要素ＩＣ、２は
インバータＩＣ、３は同期クロツクＩＣ、４はフ
リツプフロツプＩＣ、５はバツフアＩＣ、Ａは同
期クロツク信号、Ｂはバス使用可信号、Ｃはバス
要求信号、Ｄはバス獲得信号である。
FIG. 1 shows an embodiment of the bus control circuit of the present invention. In the figure, 1 is an OR element IC, 2 is an inverter IC, 3 is a synchronous clock IC, 4 is a flip-flop IC, 5 is a buffer IC, A is a synchronous clock signal, B is a bus enable signal, C is a bus request signal, D is a bus acquisition signal.
Claims (1)
於いて、バス要求信号のあるＣＰＵのフリツプフ
ロツプの内、優先順位の最も高いＣＰＵに対応す
るフリツプフロツプのみを動作可能状態とし、か
つバス使用可信号がある時のみ、ＣＰＵと同期す
る同期クロツクによつて前記フリツプフロツプを
反転させて、該当ＣＰＵにバス獲得信号を送出す
ると共に他のＣＰＵのバス使用可信号を停止せし
める様にしたバスコントロール回路。 In a circuit where multiple CPUs are connected on the same bus, only the flip-flop corresponding to the CPU with the highest priority among the flip-flops of the CPU with the bus request signal is enabled, and the bus enable signal is Only at certain times, the flip-flop is inverted by a synchronization clock that is synchronized with a CPU, and a bus acquisition signal is sent to the CPU in question, while bus enable signals of other CPUs are stopped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2311890U JPH03113444U (en) | 1990-03-07 | 1990-03-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2311890U JPH03113444U (en) | 1990-03-07 | 1990-03-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03113444U true JPH03113444U (en) | 1991-11-20 |
Family
ID=31526117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2311890U Pending JPH03113444U (en) | 1990-03-07 | 1990-03-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03113444U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57108914A (en) * | 1980-12-25 | 1982-07-07 | Fuji Electric Co Ltd | Control system for right of using bus |
-
1990
- 1990-03-07 JP JP2311890U patent/JPH03113444U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57108914A (en) * | 1980-12-25 | 1982-07-07 | Fuji Electric Co Ltd | Control system for right of using bus |
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