JPS57108914A - Control system for right of using bus - Google Patents

Control system for right of using bus

Info

Publication number
JPS57108914A
JPS57108914A JP18280280A JP18280280A JPS57108914A JP S57108914 A JPS57108914 A JP S57108914A JP 18280280 A JP18280280 A JP 18280280A JP 18280280 A JP18280280 A JP 18280280A JP S57108914 A JPS57108914 A JP S57108914A
Authority
JP
Japan
Prior art keywords
bus
signal
flip
turns
processor part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18280280A
Other languages
Japanese (ja)
Other versions
JPS6019022B2 (en
Inventor
Masahiro Yoshida
Keiichi Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP18280280A priority Critical patent/JPS6019022B2/en
Publication of JPS57108914A publication Critical patent/JPS57108914A/en
Publication of JPS6019022B2 publication Critical patent/JPS6019022B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To realize control over the right of using a bus between processors which operate asynchronously, by giving characteristic clock periods to the respective processors. CONSTITUTION:When no bus request is generated and a signal BG outputted by an AND gate 26 is at an H, a bus request REQ from a processor part P sets a flip-flop 30, whose output 30Q goes up to the H. When a bus is not in use, a flip-flop 31 is set and its output 31Q goes up to the H. Then, a signal BSy is outputted to the bus, which is acquired. A signal PMT is sent to a processor part P, which is informed that the bus is usable. Once finishing using the bus, the processor part P turns off the bus-use request REQ, turns off the flip-flops 30 and 31, and turns off the signal BSy.
JP18280280A 1980-12-25 1980-12-25 Bus right control method Expired JPS6019022B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18280280A JPS6019022B2 (en) 1980-12-25 1980-12-25 Bus right control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18280280A JPS6019022B2 (en) 1980-12-25 1980-12-25 Bus right control method

Publications (2)

Publication Number Publication Date
JPS57108914A true JPS57108914A (en) 1982-07-07
JPS6019022B2 JPS6019022B2 (en) 1985-05-14

Family

ID=16124671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18280280A Expired JPS6019022B2 (en) 1980-12-25 1980-12-25 Bus right control method

Country Status (1)

Country Link
JP (1) JPS6019022B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180352A (en) * 1984-09-27 1986-04-23 Fujitsu Ltd Multiprocessor control system
JPH03113444U (en) * 1990-03-07 1991-11-20

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180352A (en) * 1984-09-27 1986-04-23 Fujitsu Ltd Multiprocessor control system
JPH0210980B2 (en) * 1984-09-27 1990-03-12 Fujitsu Ltd
JPH03113444U (en) * 1990-03-07 1991-11-20

Also Published As

Publication number Publication date
JPS6019022B2 (en) 1985-05-14

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