JPS5638657A - Multiprocessor control system - Google Patents

Multiprocessor control system

Info

Publication number
JPS5638657A
JPS5638657A JP11418879A JP11418879A JPS5638657A JP S5638657 A JPS5638657 A JP S5638657A JP 11418879 A JP11418879 A JP 11418879A JP 11418879 A JP11418879 A JP 11418879A JP S5638657 A JPS5638657 A JP S5638657A
Authority
JP
Japan
Prior art keywords
processor
clock signal
clock
local
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11418879A
Other languages
Japanese (ja)
Other versions
JPS5832428B2 (en
Inventor
Kenji Shioda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54114188A priority Critical patent/JPS5832428B2/en
Publication of JPS5638657A publication Critical patent/JPS5638657A/en
Publication of JPS5832428B2 publication Critical patent/JPS5832428B2/en
Expired legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To enable to ensure synchronism, by stopping the supply of clock signal of other processors, when the input and output instruction is made to other processors, in the multiprocessor system operated with the common clock signal.
CONSTITUTION: The fundamental processor 1 made up of the main processor 2 and clock generator 3 and the I/O controllers 8, 9 consisting of the local processor 6, local memory 5, and clock control circuit 7 are commonly connected and the entire system is acted like the multiprocessor system with the clock signal from the fundamental processor 1. When the input and output instruction is made assynchronizyingly from the main processor 2 to the local processor 6, the supply of clock signal to the local processor 6 is temporarily stopped at the clock control circuit 7 and control is made so that the synchronism for instruction givig and reception can be taken.
COPYRIGHT: (C)1981,JPO&Japio
JP54114188A 1979-09-07 1979-09-07 Multiprocessor control method Expired JPS5832428B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54114188A JPS5832428B2 (en) 1979-09-07 1979-09-07 Multiprocessor control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54114188A JPS5832428B2 (en) 1979-09-07 1979-09-07 Multiprocessor control method

Publications (2)

Publication Number Publication Date
JPS5638657A true JPS5638657A (en) 1981-04-13
JPS5832428B2 JPS5832428B2 (en) 1983-07-13

Family

ID=14631394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54114188A Expired JPS5832428B2 (en) 1979-09-07 1979-09-07 Multiprocessor control method

Country Status (1)

Country Link
JP (1) JPS5832428B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593676A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Interprocessor clock synchronization system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593676A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Interprocessor clock synchronization system

Also Published As

Publication number Publication date
JPS5832428B2 (en) 1983-07-13

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