JPH0486346U - - Google Patents

Info

Publication number
JPH0486346U
JPH0486346U JP1990130203U JP13020390U JPH0486346U JP H0486346 U JPH0486346 U JP H0486346U JP 1990130203 U JP1990130203 U JP 1990130203U JP 13020390 U JP13020390 U JP 13020390U JP H0486346 U JPH0486346 U JP H0486346U
Authority
JP
Japan
Prior art keywords
cpu
circuit
sent
operated
controls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990130203U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990130203U priority Critical patent/JPH0486346U/ja
Publication of JPH0486346U publication Critical patent/JPH0486346U/ja
Pending legal-status Critical Current

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Landscapes

  • Microcomputers (AREA)
  • Transceivers (AREA)
  • Mobile Radio Communication Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例による制御回路を
示す回路図、第2図はこの考案の他の実施例を示
す回路図、第3図は従来の制御回路を示す図であ
る。 図において、1はCPU、2はシリアル信号デ
ータポート、3はシリアル信号クロツクポート、
4はシリアル信号ストローブポート、5〜7はI
C、8はパラレル信号、9は同期シリアル出力部
である。なお、図中、同一符号は同一、または相
当部分を示す。
FIG. 1 is a circuit diagram showing a control circuit according to one embodiment of this invention, FIG. 2 is a circuit diagram showing another embodiment of this invention, and FIG. 3 is a diagram showing a conventional control circuit. In the figure, 1 is a CPU, 2 is a serial signal data port, 3 is a serial signal clock port,
4 is serial signal strobe port, 5-7 are I
C and 8 are parallel signals, and 9 is a synchronous serial output section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] システム全体の制御を行うCPUからの入出力
信号によつて操作される複数のICによつて構成
された回路において、各IC内にLATCH回路
を持たせることにより、CPUよりシリアルデー
タを送出することによつて、同一ポートより複数
の制御機能を持たせることを特徴とする携帯用無
線機制御回路。
In a circuit composed of multiple ICs that are operated by input/output signals from the CPU that controls the entire system, by providing a LATCH circuit in each IC, serial data can be sent from the CPU. A portable radio control circuit characterized in that multiple control functions can be provided from the same port.
JP1990130203U 1990-11-30 1990-11-30 Pending JPH0486346U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990130203U JPH0486346U (en) 1990-11-30 1990-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990130203U JPH0486346U (en) 1990-11-30 1990-11-30

Publications (1)

Publication Number Publication Date
JPH0486346U true JPH0486346U (en) 1992-07-27

Family

ID=31877563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990130203U Pending JPH0486346U (en) 1990-11-30 1990-11-30

Country Status (1)

Country Link
JP (1) JPH0486346U (en)

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