JPH0267441U - - Google Patents
Info
- Publication number
- JPH0267441U JPH0267441U JP14406288U JP14406288U JPH0267441U JP H0267441 U JPH0267441 U JP H0267441U JP 14406288 U JP14406288 U JP 14406288U JP 14406288 U JP14406288 U JP 14406288U JP H0267441 U JPH0267441 U JP H0267441U
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- signal line
- serial data
- shift
- register connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
第１図は本考案の一実施例を示すシリアルデー
タ受信回路図である。
１……第一のシフトレジスタ、２……第二のシ
フトレジスタ、３……ラツチ回路、４……エクス
クルーシブＯＲ回路、５……ＮＯＲ回路、６……
ＡＮＤ回路、７……シリアルデータ信号線、８…
…クロツク信号線、９……ストローブ信号線、１
０……判定信号線。
FIG. 1 is a serial data receiving circuit diagram showing an embodiment of the present invention. 1...First shift register, 2...Second shift register, 3...Latch circuit, 4...Exclusive OR circuit, 5...NOR circuit, 6...
AND circuit, 7... Serial data signal line, 8...
...Clock signal line, 9...Strobe signal line, 1
0...Judgment signal line.
Claims (1)
接続された第一のシフトレジスタと、前記第一の
シフトレジスタに接続された第二のシフトレジス
タと、これら両シフトレジスタに転送されたシリ
アルデータを比較する手段と、前記第一および第
二のシフトレジスタの内容が一致する時にのみデ
ータラツチを行うラツチ回路とを有することを特
徴とするシリアルデータ受信回路。 A first shift register connected to a serial data signal line and a clock signal line, a second shift register connected to the first shift register, and means for comparing serial data transferred to both shift registers. and a latch circuit that latches data only when the contents of the first and second shift registers match.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14406288U JPH0267441U (en) | 1988-11-02 | 1988-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14406288U JPH0267441U (en) | 1988-11-02 | 1988-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0267441U true JPH0267441U (en) | 1990-05-22 |
Family
ID=31411440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14406288U Pending JPH0267441U (en) | 1988-11-02 | 1988-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0267441U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05120162A (en) * | 1991-10-28 | 1993-05-18 | Mitsubishi Electric Corp | Noise eliminating circuit |
-
1988
- 1988-11-02 JP JP14406288U patent/JPH0267441U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05120162A (en) * | 1991-10-28 | 1993-05-18 | Mitsubishi Electric Corp | Noise eliminating circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0267441U (en) | ||
| JPS62147041U (en) | ||
| JPH03106600U (en) | ||
| JPH0486346U (en) | ||
| JPH0276398U (en) | ||
| JPS63168549U (en) | ||
| JPH03117947U (en) | ||
| JPS6356454U (en) | ||
| JPS63155552U (en) | ||
| JPS61196345U (en) | ||
| JPS62138253U (en) | ||
| JPH01142054U (en) | ||
| JPS601037U (en) | binary circuit | |
| JPS62117797U (en) | ||
| JPH0221823U (en) | ||
| JPS6281252U (en) | ||
| JPH0374315U (en) | ||
| JPS63126944U (en) | ||
| JPS61180303U (en) | ||
| JPS6384651U (en) | ||
| JPS5890405U (en) | I/O auxiliary device for sequencer | |
| JPS61192353U (en) | ||
| JPH03119202U (en) | ||
| JPS58124827U (en) | Cyclic data transmission device | |
| JPH01142031U (en) |