JPS6384651U - - Google Patents
Info
- Publication number
- JPS6384651U JPS6384651U JP17878286U JP17878286U JPS6384651U JP S6384651 U JPS6384651 U JP S6384651U JP 17878286 U JP17878286 U JP 17878286U JP 17878286 U JP17878286 U JP 17878286U JP S6384651 U JPS6384651 U JP S6384651U
- Authority
- JP
- Japan
- Prior art keywords
- lsi
- signal
- circuit
- slave
- serial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Information Transfer Systems (AREA)
Description
第１図は本考案実施例の回路構成を示す図、第
２図は本考案実施例の信号波形を示す図、第３図
は本考案を適用したシステムの構成を示す図、第
４図は従来のシステムの構成を示す図、第５図は
従来の信号波形を示す図である。
１，２…ＬＳＩ、３…出力ラツチ、４…入／出
力切換ラツチ、５…ノアゲート、６…ＦＥＴ、７
…インバータ、１０…８ビツトカウンタ、１２…
ＲＤＹ／ＣＬＫ端子、１３…信号線。
FIG. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a diagram showing signal waveforms of the embodiment of the present invention, FIG. 3 is a diagram showing the configuration of a system to which the present invention is applied, and FIG. A diagram showing the configuration of a conventional system, and FIG. 5 is a diagram showing conventional signal waveforms. 1, 2...LSI, 3...Output latch, 4...Input/output switching latch, 5...Nor gate, 6...FET, 7
...Inverter, 10...8-bit counter, 12...
RDY/CLK terminal, 13...signal line.
Claims (1)
出力するとスレーブＬＳＩが出力するクロツクに
同期してシリアルデータをマスターＬＳＩとスレ
ーブＬＳＩとの間で送受するシリアルＩ／Ｏ回路
において、マスターＬＳＩがスレーブＬＳＩに対
してクロツクの出力を許可及び禁止する信号を１
本の信号線に出力する信号出力回路と、上記信号
に応じてスレーブＬＳＩから上記信号線に出力さ
れたクロツクを受けるクロツク入力回路とを備え
たことを特徴とするシリアルＩ／Ｏ回路。 In a serial I/O circuit that sends and receives serial data between the master LSI and slave LSI in synchronization with the clock output by the slave LSI when the master LSI outputs a signal requesting data transfer, the master LSI transfers data to and from the slave LSI. 1 signal to enable and disable clock output.
1. A serial I/O circuit comprising: a signal output circuit for outputting to a main signal line; and a clock input circuit for receiving a clock output from a slave LSI to the signal line in response to the signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17878286U JPS6384651U (en) | 1986-11-20 | 1986-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17878286U JPS6384651U (en) | 1986-11-20 | 1986-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6384651U true JPS6384651U (en) | 1988-06-03 |
Family
ID=31121236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17878286U Pending JPS6384651U (en) | 1986-11-20 | 1986-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6384651U (en) |
-
1986
- 1986-11-20 JP JP17878286U patent/JPS6384651U/ja active Pending
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