JPS5885222U

JPS5885222U - digital controller

Info

Publication number: JPS5885222U
Application number: JP18009881U
Authority: JP
Inventors: 敏彦小倉; 正弘高橋
Original assignee: 株式会社日立製作所
Priority date: 1981-12-04
Filing date: 1981-12-04
Publication date: 1983-06-09

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来のデジタルコントローラのブロック図、第
２図は本考案の一実施例のデジタルコントローラのブロ
ック図である。１０・・・プロセッサ、２Ｇ、２１．２２・・・メモリ
ー、３０・・・回線対応部、４０・・・ＤＭＡ制御部、
５０・・・モデム、６０・・・バス切換え制御回路、７
０・・・バス切換え回路、８０・・・バスインターフェ
イス回路、８１・・・フリップフロップ、８２・・・イ
ンバータ、９０．９１，９２．９３・・・バスゲート、
ｂ−１・・・プロセッサバス、ｂ−２・・・データ転送
バス、１・・・伝送回線、Ｃ１・・・プロセッサアクセ
ス要求信号、Ｃ２・・・ＤＭＡ制御部転送要求信号、Ｃ
３・・・バス切換え制御信号。FIG. 1 is a block diagram of a conventional digital controller, and FIG. 2 is a block diagram of a digital controller according to an embodiment of the present invention. 10... Processor, 2G, 21.22... Memory, 30... Line support unit, 40... DMA control unit,
50...Modem, 60...Bus switching control circuit, 7
0... Bus switching circuit, 80... Bus interface circuit, 81... Flip-flop, 82... Inverter, 90.91, 92.93... Bus gate,
b-1... Processor bus, b-2... Data transfer bus, 1... Transmission line, C1... Processor access request signal, C2... DMA control unit transfer request signal, C
3...Bus switching control signal.

Claims

[Scope of utility model registration request]

A DM that interfaces the processor, memory, processor bus, data transfer bus, and the outside world.
A digital controller comprising an input/output unit having the A function, and the memory have connection means for connecting the processor bus and each of the data transfer buses, and this connection means performs DMA transfer based on the DMA function. Sometimes, the memory and the processor bus are separated, the memory and the data transfer bus are connected, and data is transferred between the input/output section and the memory via the data transfer bus, and the memory is transferred by the processor. At the time of access, the memory and the data transfer bus are separated, the memory and the processor bus are connected, and data is transferred between the processor and the memory via the processor bus. digital controller.