JPS6034652U - information transfer device - Google Patents
information transfer deviceInfo
- Publication number
- JPS6034652U JPS6034652U JP10840884U JP10840884U JPS6034652U JP S6034652 U JPS6034652 U JP S6034652U JP 10840884 U JP10840884 U JP 10840884U JP 10840884 U JP10840884 U JP 10840884U JP S6034652 U JPS6034652 U JP S6034652U
- Authority
- JP
- Japan
- Prior art keywords
- input
- control circuit
- dedicated control
- processing unit
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の情報転送装置の構成を示すブロック図、
第２図は本考案の情報転送装置の一実施例の構成を示す
ブロック図、第３図は優先回路の一構成例を示す図であ
る。
１・・・入出力装置専用ＬＳＩ、２・・・８ビツトバツ
フアレジスタ、３・・・メインメモリ、４・・・中央処
理装置（ＣＰＵ） 、５・・・情報交換用レジスタ、１
１・・・優先回路、１２・・・３進カウンタ、１３・・
・ＤＭＡ制御回路、１４・・・フリップフロップ、１５
・・・遅延回路。
ｒ４
３．−Ｘｌ
″［−
，１１FIG. 1 is a block diagram showing the configuration of a conventional information transfer device.
FIG. 2 is a block diagram showing the configuration of an embodiment of the information transfer device of the present invention, and FIG. 3 is a diagram showing an example of the configuration of the priority circuit. 1... LSI dedicated to input/output device, 2... 8-bit buffer register, 3... Main memory, 4... Central processing unit (CPU), 5... Register for information exchange, 1
1... Priority circuit, 12... Ternary counter, 13...
・DMA control circuit, 14...Flip-flop, 15
...Delay circuit. r4 3. −Xl″[−,11
Claims (1)
路と８ビツトバツフアレジスタとを具え中央処理装置の
制御に応じて１６ビツト単位で情報を転送する情報転送
装置はおいて、前記入出力装置専用制御回路に情報交換
用レジスタを具えるとともに、前記入出力装置専用制御
回路と中央処理装置との動作の優先性を定め１６ビツト
のデータを組立て中および分割して入出力装置専用制御
回路に入力する間は前記中央処理装置から該情報交換用
レジスタへのアクセスを保留し、中央処理装置が入出力
装置専用制御回路に対してアクセス中は１６ビツトのデ
ータの組立ておよび分割入力を保留する優先回路を有す
ることを特徴とする情報転送装置。An information transfer device is equipped with a dedicated control circuit for an input/output device capable of outputting information in units of 8 bits and an 8-bit buffer register, and transfers information in units of 16 bits under the control of a central processing unit. The dedicated control circuit is equipped with a register for information exchange, and also determines the priority of operation between the input/output device dedicated control circuit and the central processing unit, and 16-bit data is assembled and divided into the input/output device dedicated control circuit. Priority is given to suspending access from the central processing unit to the information exchange register during input, and suspending assembly and division input of 16-bit data while the central processing unit is accessing the input/output device dedicated control circuit. An information transfer device characterized by having a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10840884U JPS6034652U (en) | 1984-07-18 | 1984-07-18 | information transfer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10840884U JPS6034652U (en) | 1984-07-18 | 1984-07-18 | information transfer device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6034652U true JPS6034652U (en) | 1985-03-09 |
Family
ID=30252931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10840884U Pending JPS6034652U (en) | 1984-07-18 | 1984-07-18 | information transfer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6034652U (en) |
-
1984
- 1984-07-18 JP JP10840884U patent/JPS6034652U/en active Pending
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