JPS6039139U - Magnetic card reader interface circuit - Google Patents

Magnetic card reader interface circuit

Info

Publication number
JPS6039139U
JPS6039139U JP12724583U JP12724583U JPS6039139U JP S6039139 U JPS6039139 U JP S6039139U JP 12724583 U JP12724583 U JP 12724583U JP 12724583 U JP12724583 U JP 12724583U JP S6039139 U JPS6039139 U JP S6039139U
Authority
JP
Japan
Prior art keywords
magnetic card
interface circuit
card reader
reader interface
card league
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12724583U
Other languages
Japanese (ja)
Inventor
慎治 石井
吉田　敏治
Original Assignee
日通工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日通工株式会社 filed Critical 日通工株式会社
Priority to JP12724583U priority Critical patent/JPS6039139U/en
Publication of JPS6039139U publication Critical patent/JPS6039139U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の磁気カードリーグインタフェースの読取
り回路の構成を示すブロック図、第２図は本考案に係る
磁気カードリーグインタフェースの読取り回路の構成を
示すブロック図、第３図は磁気カードリーグの読取り部
会信号のタイミングチャート図、第４図はシリアル通信
用ＬＳＩの内部構成を示すブロック図である。 図中、１は磁気カードリーグ、２は並列入出力ＬＳＩ、
３はＣＰＵ、４はＲＡＭ、５はカウンタ、６はＯＲゲー
ト、７はゲート、８はシリアル通信用ＬＳＩである。Figure 1 is a block diagram showing the configuration of a reading circuit of a conventional magnetic card league interface, Figure 2 is a block diagram showing the configuration of a reading circuit of a magnetic card league interface according to the present invention, and Figure 3 is a block diagram showing the configuration of a reading circuit of a magnetic card league interface according to the present invention. A timing chart of reading group signals and FIG. 4 are block diagrams showing the internal configuration of the serial communication LSI. In the figure, 1 is a magnetic card league, 2 is a parallel input/output LSI,
3 is a CPU, 4 is a RAM, 5 is a counter, 6 is an OR gate, 7 is a gate, and 8 is an LSI for serial communication.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 磁気カードリーグと中央演算処理装置バスとのインタフ
ェース部に、シリアル通信用ＬＳＩを使用したことを特
徴とする磁気カードリーグのインタフェース回路。A magnetic card league interface circuit characterized in that a serial communication LSI is used in an interface section between the magnetic card league and a central processing unit bus.
JP12724583U 1983-08-19 1983-08-19 Magnetic card reader interface circuit Pending JPS6039139U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12724583U JPS6039139U (en) 1983-08-19 1983-08-19 Magnetic card reader interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12724583U JPS6039139U (en) 1983-08-19 1983-08-19 Magnetic card reader interface circuit

Publications (1)

Publication Number Publication Date
JPS6039139U true JPS6039139U (en) 1985-03-18

Family

ID=30289068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12724583U Pending JPS6039139U (en) 1983-08-19 1983-08-19 Magnetic card reader interface circuit

Country Status (1)

Country Link
JP (1) JPS6039139U (en)

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