JPS58105640U - Data conversion device between different buses - Google Patents
Data conversion device between different busesInfo
- Publication number
- JPS58105640U JPS58105640U JP328182U JP328182U JPS58105640U JP S58105640 U JPS58105640 U JP S58105640U JP 328182 U JP328182 U JP 328182U JP 328182 U JP328182 U JP 328182U JP S58105640 U JPS58105640 U JP S58105640U
- Authority
- JP
- Japan
- Prior art keywords
- data
- bus
- conversion device
- different buses
- bit length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデータ変換の原理を説明する説明図、第
２図は第１図に基づくビット長変換の操作手順を示す説
明図、第３図は本考案に係る異なるバス間のデータ変換
装置の原理を説明する説明図、第４図は第３図の原理説
明に基づく本考案の一実施例を示すブロック図、第５図
Ａ、 Ｂは本考案のピッド長変換の操作手順を示す説明
図、第６図Ａ、 Ｂは第５図Ａ、 Ｂに基づ（ビット長
変換の操作手順を一般化した場合の説明図、第７図は第
６図の操作手順を実行するためのフローである。
１・・・インターフェース回路、２・・・コントロール
部、３１〜３Ｎ・・・バッファゲート、４１〜４Ｎ・・
・コントロール信号、ａ′・・・Ａビットバス、ｂ′…
Ａ×Ｎビットバス、ａ′・・・上位バスの制御信号もし
くはアドレス、Ｗ１〜ＷＮ・・・収集ワード。
第６図 。Fig. 1 is an explanatory diagram explaining the principle of conventional data conversion, Fig. 2 is an explanatory diagram showing the operating procedure of bit length conversion based on Fig. 1, and Fig. 3 is an explanatory diagram showing the operation procedure of bit length conversion based on Fig. 1. Fig. 3 is an explanatory diagram explaining the principle of conventional data conversion. An explanatory diagram for explaining the principle of the device, Fig. 4 is a block diagram showing an embodiment of the present invention based on the explanation of the principle in Fig. 3, and Figs. 5 A and B show the operating procedure of pit length conversion of the present invention. Explanatory diagrams, Figures 6A and B are based on Figures 5A and B (explanatory diagrams when the operating procedure of bit length conversion is generalized, and Figure 7 is a diagram for carrying out the operating procedure of Figure 6). The flow is: 1...Interface circuit, 2...Control section, 31-3N...Buffer gate, 41-4N...
・Control signal, a'...A bit bus, b'...
A×N bit bus, a'...control signal or address of upper bus, W1-WN...collection word. Figure 6.
Claims (2)
のビット長変換を行う装置において、前記上位バスと下
位バス間に複数個の下位バスデータを収集するエリアを
有するインターフェース回路を介して前記上位バスから
下位バスをアクセスすることにより下位ビット長のデー
タを上位ビット長のデータに変換することを特徴とする
゛ 異なるバス間のデータ変換装置。(1) In a device in which an upper bus accesses a lower bus and performs bit length conversion between bus data and data, the 1. A data conversion device between different buses, which converts data with a lower bit length into data with a higher bit length by accessing a lower bus from an upper bus.
タの収集ワード毎に複数個並列接続されたバッファゲー
トと、各バッファゲートを対応する下位バスデータの収
集ツー５ドに応じてコントロールするコントロール信号
を前記上位バスの制御信号もしくはアドレス信号に基づ
いて送出するコントロール部とからなるーことを特徴と
する実用新案登録請求の範囲第１項記載の異なるバス間
のデータ変換装置。(2) The interface circuit includes a plurality of buffer gates connected in parallel for each collection word of the lower bus data, and a control signal for controlling each buffer gate according to the collection word of the corresponding lower bus data. 2. The data conversion device between different buses according to claim 1, characterized in that the device comprises a control section that sends data based on a control signal or an address signal of a higher-level bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP328182U JPS58105640U (en) | 1982-01-14 | 1982-01-14 | Data conversion device between different buses |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP328182U JPS58105640U (en) | 1982-01-14 | 1982-01-14 | Data conversion device between different buses |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58105640U true JPS58105640U (en) | 1983-07-18 |
Family
ID=30016223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP328182U Pending JPS58105640U (en) | 1982-01-14 | 1982-01-14 | Data conversion device between different buses |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58105640U (en) |
-
1982
- 1982-01-14 JP JP328182U patent/JPS58105640U/en active Pending
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