JPS60164252U - data processing equipment - Google Patents

data processing equipment

Info

Publication number
JPS60164252U
JPS60164252U JP4136385U JP4136385U JPS60164252U JP S60164252 U JPS60164252 U JP S60164252U JP 4136385 U JP4136385 U JP 4136385U JP 4136385 U JP4136385 U JP 4136385U JP S60164252 U JPS60164252 U JP S60164252U
Authority
JP
Japan
Prior art keywords
storage
address
data processing
storage device
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4136385U
Other languages
Japanese (ja)
Other versions
JPS625727Y2 (en
Inventor
英晴 小林
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP4136385U priority Critical patent/JPS60164252U/en
Publication of JPS60164252U publication Critical patent/JPS60164252U/en
Application granted granted Critical
Publication of JPS625727Y2 publication Critical patent/JPS625727Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はデータ処理装置の一般的構成を示すブロック図
、第2図は従来の記憶拡張の概念を示すブロック図、第
3図は論理記憶装置と物理記憶装置との対応例を示す図
、第4図はプログラム実行中におけるチャネル装置によ
るデータの転送時間関係を示す図、第5図はこの考案に
よるデータ処理装置における記憶拡張概惹図、第6図は
第5図の記憶拡張における論理記憶装置と物理記憶装置
との対応例を示す図、第7図は変換記憶部のビ″/′−
ト配列の例を示す図、第8図は物理記憶アドレスの作成
を示すブロック図である。          ′1:
主記憶装置、2:中央制御装置、3〜5:チャネル装置
、2a、2b:バス、10:論理記憶アドレスレジスタ
、11:論理記憶装置、1  ゛2:物理記憶アドレス
レジスタ、131理記憶装置、14.1400〜141
7:変換記憶部、15:メモリ制御レジスタ。
FIG. 1 is a block diagram showing the general configuration of a data processing device, FIG. 2 is a block diagram showing the concept of conventional storage expansion, and FIG. 3 is a diagram showing an example of correspondence between a logical storage device and a physical storage device. Fig. 4 is a diagram showing the data transfer time relationship by the channel device during program execution, Fig. 5 is a schematic diagram of memory expansion in the data processing device according to this invention, and Fig. 6 is the logical storage in the memory expansion of Fig. 5. A diagram showing an example of correspondence between a device and a physical storage device, FIG.
FIG. 8 is a block diagram showing the creation of physical storage addresses. '1:
Main storage device, 2: Central control unit, 3 to 5: Channel device, 2a, 2b: Bus, 10: Logical storage address register, 11: Logical storage device, 1 2: Physical storage address register, 131 Physical storage device, 14.1400-141
7: Conversion storage unit, 15: Memory control register.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 論理記憶の各アドレスを指定する論理アドレスにより指
定可能な容量よりも大きな記憶容量を持ち、複数の物理
記憶装置からなる主記憶装置と、中央制御装置と、チャ
ネル装置とからなるデータ処理装置において、上記主記
憶装置の論理記憶装置アドレスから物理記憶装置アドレ
スに変換する情報を貯蔵し、命令により書込み可能な上
記主記憶装置のアドレス空間とは異なる変換記憶部が上
記中央制御装置用として複数段けられ、これら複数の変
換記憶部のどの変換記憶部を使用するかは命令により指
定可能とし、上記各チャネル装置用として上記変換記憶
部をそれぞれに1個設けてなるデータ処理装置。
In a data processing device that has a storage capacity larger than the capacity that can be specified by a logical address that specifies each address of logical storage, and that consists of a main storage device consisting of a plurality of physical storage devices, a central control device, and a channel device, A conversion storage section different from the address space of the main storage device that stores information for converting a logical storage device address of the main storage device into a physical storage device address and that can be written in by a command is arranged in multiple stages for the central control unit. A data processing device, wherein one of the plurality of conversion storage units can be specified by a command to be used, and one conversion storage unit is provided for each of the channel devices.
JP4136385U 1985-03-22 1985-03-22 data processing equipment Granted JPS60164252U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4136385U JPS60164252U (en) 1985-03-22 1985-03-22 data processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4136385U JPS60164252U (en) 1985-03-22 1985-03-22 data processing equipment

Publications (2)

Publication Number Publication Date
JPS60164252U true JPS60164252U (en) 1985-10-31
JPS625727Y2 JPS625727Y2 (en) 1987-02-09

Family

ID=30551115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4136385U Granted JPS60164252U (en) 1985-03-22 1985-03-22 data processing equipment

Country Status (1)

Country Link
JP (1) JPS60164252U (en)

Also Published As

Publication number Publication date
JPS625727Y2 (en) 1987-02-09

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