JPS62134151U - - Google Patents

Info

Publication number
JPS62134151U
JPS62134151U JP7794086U JP7794086U JPS62134151U JP S62134151 U JPS62134151 U JP S62134151U JP 7794086 U JP7794086 U JP 7794086U JP 7794086 U JP7794086 U JP 7794086U JP S62134151 U JPS62134151 U JP S62134151U
Authority
JP
Japan
Prior art keywords
address
storage device
storage
logical
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7794086U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7794086U priority Critical patent/JPS62134151U/ja
Publication of JPS62134151U publication Critical patent/JPS62134151U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はデータ処理装置の一般的構成を示すブ
ロツク図、第2図は従来の記憶拡張の概念を示す
ブロツク図、第3図は論理記憶装置と物理記憶装
置との対応側を示す図、第4図はプログラム実行
中におけるチヤネル装置によるデータの転送時間
関係を示す図、第5図はこの考案によるデータ処
理装置における記憶拡張概念図、第6図は第5図
の記憶拡張における論理記憶装置と物理記憶装置
との対応例を示す図、第7図は変換記憶部のビツ
ト配列の例を示す図、第8図は物理記憶アドレス
の作成を示すブロツク図である。 1:主記憶装置、2:中央制御装置、3〜5:
チヤネル装置、2a,2b:バス、10:論理記
憶アドレスレジスタ、11:論理記憶装置、12
:物理記憶アドレスレジスタ、13:物理記憶装
置、14,1400〜1417:変換記憶部、1
5:メモリ制御レジスタ。
FIG. 1 is a block diagram showing the general configuration of a data processing device, FIG. 2 is a block diagram showing the concept of conventional storage expansion, and FIG. 3 is a diagram showing the correspondence between a logical storage device and a physical storage device. Fig. 4 is a diagram showing the data transfer time relationship by the channel device during program execution, Fig. 5 is a conceptual diagram of storage expansion in the data processing device according to this invention, and Fig. 6 is a logical storage device in the storage expansion of Fig. 5. FIG. 7 is a diagram showing an example of the bit arrangement of the conversion storage section, and FIG. 8 is a block diagram showing the creation of a physical storage address. 1: Main memory, 2: Central control unit, 3 to 5:
Channel device, 2a, 2b: Bus, 10: Logical storage address register, 11: Logical storage device, 12
: Physical storage address register, 13: Physical storage device, 14, 1400 to 1417: Conversion storage unit, 1
5: Memory control register.

Claims (1)

【実用新案登録請求の範囲】 論理記憶の各アドレスを指定する論理アドレス
により指定可能な容量よりも大きな記憶容量を持
ち、物理記憶装置からなる主記憶装置と、中央制
御装置と、チヤネル装置とを備えるデータ処理装
置において、 論理記憶装置アドレスから物理記憶装置アドレ
スに変換する情報を貯蔵し、前記主記憶装置のア
ドレス空間とは異なるアドレス空間を有し、命令
により書込み可能な変換記憶部を、前記中央制御
装置用に複数面、および前記各チヤネル装置用に
それぞれ1面づつ設け、 メモリ制御レジスタの内容により前記中央制御
装置用の変換記憶部の一つを選択し、その変換記
憶部の内容により論理記憶装置アドレスから物理
記憶装置アドレスへの変換を行なうことを特徴と
するデータ処理装置。
[Claims for Utility Model Registration] A main storage device consisting of a physical storage device, a central control device, and a channel device that has a storage capacity larger than the capacity that can be specified by the logical address that specifies each address of the logical storage. A data processing device comprising: a conversion storage section that stores information for converting a logical storage device address to a physical storage device address, has an address space different from an address space of the main storage device, and is writable by a command; A plurality of planes are provided for the central control unit, and one plane is provided for each of the channel devices, one of the conversion storage units for the central control unit is selected according to the contents of the memory control register, and one of the conversion storage units is selected according to the contents of the conversion storage unit. A data processing device that converts a logical storage device address into a physical storage device address.
JP7794086U 1986-05-23 1986-05-23 Pending JPS62134151U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7794086U JPS62134151U (en) 1986-05-23 1986-05-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7794086U JPS62134151U (en) 1986-05-23 1986-05-23

Publications (1)

Publication Number Publication Date
JPS62134151U true JPS62134151U (en) 1987-08-24

Family

ID=30926421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7794086U Pending JPS62134151U (en) 1986-05-23 1986-05-23

Country Status (1)

Country Link
JP (1) JPS62134151U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51118928A (en) * 1975-03-24 1976-10-19 Hewlett Packard Yokogawa Memory expandor
JPS522231A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Information processing apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51118928A (en) * 1975-03-24 1976-10-19 Hewlett Packard Yokogawa Memory expandor
JPS522231A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Information processing apparatus

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