JPS5946012B2 - Data transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a memory device with a word addressing system in which one word consists of n bytes (n = 2, positive integer) and an input/output device with an independent byte addressing system. The present invention relates to a data transfer control method between the computer and the computer, and in particular to a transfer control method for improving the efficiency of storage device usage.

If a byte address specified by an input/output device is directly transferred as a word address to a storage device, a blank space will be created in the transfer area of the storage device, which has the disadvantage that the storage capacity cannot be used effectively.

That is, conventionally, an input/output device 10 that transfers 1 byte or 2 bytes of data using a byte address,
Memory device MM consisting of 2 bytes (16 bits) per word
Transfer between the two is performed in the form shown in FIGS. 1 and 2. Figure 1 shows the case where the input/output device (hereinafter referred to as 10) transfers one byte at a time to the storage device (hereinafter referred to as MM), and Figure 2 shows the case where 10 transfers one byte to the MM. This shows the case where data is transferred in units of 2 bytes.

In Figure 1 (as shown in thick a), the byte on the 10th side
By transferring the address using the address line and the data using the data line, the MM side uses the byte address as a word address and stores the data in the MM. For even addresses, the upper byte is '0', and for even addresses, the lower byte is '0'.
It becomes blank at 0゛, and the MM usage efficiency is halved.

In order to increase the usage efficiency of MM, AB, CD, EF,
It is necessary to programmatically configure the byte data of . . . into word data and store it again in the MM. Next, in Fig. 2, as shown in a, data on the 10 side is sent by two bytes each byte, and even addresses are sent by byte.
By transferring data through the address line, the byte address is stored in the MM as a word address, so the MM
The usage efficiency has been halved. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks when data is transferred between an input/output device and memory using a byte addressing system different from memory addresses using a word addressing system.
By converting addresses into memory addresses and editing data, the purpose is to improve memory usage efficiency and eliminate the need for programs to rearrange memory contents.

The above purpose is to transfer data between an input/output device having a byte addressing system that is independent of the memory address of the word addressing system and a storage device consisting of 1 word and n bytes. This is achieved by providing a data transfer control device between the storage devices and converting byte addresses on the input/output device side into word addresses in the storage device by the data transfer control device.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of a system in which data transfer control is performed. Between 10 and MM is a memory control device MC.
U and a data transfer control unit DTGU are connected, and these devices are activated for transfer by the central processing unit CPU.

A bus having types A, B, C, and D is extended from the data transfer control unit DTCU to the magnetic tape device M.
10 such as T and printer device PTR are connected. Bus A
is a data line for transferring 16 bits (2 bytes), bus B is a control line that specifies using bus A for 1 byte or 2 bytes (1 word), and bus C stores data on data line A. do. address lines specifying byte addresses;
Bus D is a data direction designation line indicating the data transfer direction. The data conversion control unit DTCU is 10 at a time.
When transferring data to MM in bytes, it has the function of converting the value of the C circle byte address to 1/2 and editing 2 bytes of data into one word of MM, while 10 is transferred 2 at a time.
When transferring data to the MM in units of bytes, it has a function of converting the value of the byte address to 1/2 and storing it in the MM.

FIG. 4 is a block diagram of the data transfer control device, FIG.
FIG. 6 is an explanatory diagram of the operation of the shift register in FIG. 4, and FIG. 7 is an explanatory diagram of data transfer and storage states.

First, when transferring data from O to MM in 1 byte units at a time, address AD at address 1000 of 0 in Figure 4.
is sent via the byte/address line C, the byte/word designation line B designates a byte, and the direction designation line } designates the direction from 10 to MM.

8-bit data 0A' is transferred via data line A.

The address on the byte address line C is expressed in binary coded hexadecimal notation with 16 bits each consisting of 4 bits, so it is 1000.
The address will have a code as shown in Figure 5a.

The address 1000 on the address line C is shifted one bit to the right by the shift register SR of the control unit DTCU as shown in FIGS. 6A and b, and converted to address 800 as shown in FIG. - Set in address register MAR. In FIG. 4, MM indicates a storage device, the contents of which are after data transfer from O. Note that MM indicates the contents of the storage device MM before the data transfer, and although it is shown overlapping with MM, there is no actual storage device called MM. Here, MM is accessed at address 800 of the memory address register MAR, and the contents of address 800 of MM before data transfer shown in MM8
XX'' is read. At this time, the least significant bit of the byte address from 10 is 60'' and the byte/word designation line B is byte designation, so the upper side UP of the data assemble register DAR has the upper side of the data line A. The lower-order data 1X'' of the data read from address 800 of MM is set in the lower-order LW. After that, MM is accessed again at address 800 of memory address register MAR, and data assembly ● register D
Data 1A,X'' set above AR is MM
It is stored at address 800 above. Next, the address AD at address 1001 of 10 in FIG.
After being converted to an address, the memory address register MA
Set to R.

MM at address 800 of memory address register MAR
and reads data 6A,X''. At this time, 10
Since the least significant bit of the byte address from MM is 61, and the byte/word designation line B is byte designation, the upper side UP of the DAR contains the upper data "A" of the data read from address 800 of the MM, and the lower side Data 6B1 on the lower side of data line A is set to LW. after that,
Address 800 of MM is accessed again, and 6A and B1 edited by data assemble register DAR are stored in MM.
is stored in In this way, address 1002 of 10,
Data 3 and 4 at address 1003 are transferred alternately, with the upper 8 bits and lower 8 bits, as shown in FIG. , the memory address 801 which is set alternately in the lower part LW and is edited here, and the byte address is converted into a word address.
The data is sequentially stored in the upper address area and the lower address area of 801.
Conversely, when transferring MM data to the 10 side, the byte address from 10 is transferred to 1 by shift register SR.
Access MM with the memory address shifted to the right by bits and transfer the read data to 10.

Next, when data is transferred from 10 to MM in units of 2 bytes (1 word) at a time, the address AD at address 1000 in FIG. 4 is transferred via the byte address line C,
A word designation is designated on the byte/word designation line B, and a direction from 10 to MM is designated on the direction designation line D, respectively.

"A, B" of 16-bit data DT is transferred via data line A and set in data assemble register DAR of control unit DTCU.

Address 1000 on address line C is shift register SR
After being set in the memory address register MAR, address 800 of MM is accessed and the contents of the data assembly register DAR are stored as is. Similarly, in b of Fig. 7, 10
The data 31 sent by byte address 1002 is converted by the shift register SR to the word address 801 of the MM, and is stored in the MM.

As shown in Figure 7b, byte address 1004,1
Data 5 is on data line A for address 006...
Since data 6 and 78 are transferred continuously in word units, the data is not edited and is sequentially stored in the MM only by address input conversion.

The above is an explanation of data transfer control between 10, which has a byte address, and MM, which is composed of 1 word and 2 bytes, but according to the present invention, 10, which has an address system independent of MM, and 1 word, n bytes. (n = 2K, K = positive integer) It is also applicable to a data transfer control method between MMs consisting of MMs, which prevents blank spaces from occurring in the MM area due to address conversion and data editing by the data transfer control unit DTCU. Therefore, the memory can be used effectively without deteriorating the memory usage efficiency without having to edit the data by a program.

[Brief explanation of drawings]

1 and 2 are explanatory diagrams of conventional 1-byte transfer and 2-byte transfer from the 10 side to the MM side, FIG. 3 is a block diagram of a system showing an embodiment of the present invention, and FIG. 5 and 6 are diagrams for explaining the operation of the shift register in FIG. 4, and FIG. 7 is a diagram for explaining data transfer and storage states. 10: input/output device, MM: main memory, MCU: memory control unit, CPU: central processing unit, DTCU: data transfer control unit, MT: magnetic tape device, PTR: paper tape reader, A: data line, B: Byte/word designation line,
C: Byte address line, D: Data transfer direction designation line,
DAR: Data assembly register, SR: Shift register, MAR: Memory address register, A
D: Address, DT: Data.

Claims (1)

[Claims] 1. An input/output device with a byte addressing system in which a memory address is assigned in byte units that is almost independent of the memory address of the storage device, and a word addressing system in which one word consists of n bytes and a memory address is assigned in word units. When transferring data to and from a storage device, a data transfer control device is provided between the input/output device and the storage device, and the data transfer control device controls the byte address specified by the input/output device at the time of data transfer to the storage device. A data transfer control method characterized by converting data into word addresses and transferring data between a storage device and an input/output device.