JPH11184797A - Dma controller and method therefor and recording medium for recording control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA controller in which high speed DMAI(Direct Memory Access) transfer can be attained at the time of operating DMA beyond a page boundary between pages continuous on a physical address. SOLUTION: At the time of operating DMA transfer, a page address and the number of continuous pages are obtained by referring to an address conversion table. A value obtained by adding offset to the page address is substituted for a current physical address, and data for a unit transfer size are DMA transferred. When the remaining transfer size is not 0, a value obtained by adding the unit transfer size to the offset is substituted for the offset, and when the offset is made equal to a page size, a page number is incremented, and '0' is substituted for the offset in a step S9. At that time, when the number of continuous pages is not '0', a value obtained by adding the page address to a base address is substituted for the base address, and the number of continuous pages is decremeted, and DMA transferred in a step S12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller, and more particularly to a DMA controller for a plurality of pages on a main memory.
(Direct Memory Access) control method.

[0002]

2. Description of the Related Art Conventionally, as a DMA control method, a CPU is used.
When the logical address output from the (central processing unit) is converted to a physical address by the memory management unit and the main memory is accessed, the DMA device directly transfers the physical address to the main memory without passing through the memory management unit during DMA. There is a way to output and access.

In this method, since the physical address is discontinuous in page units, it is not possible to easily perform a DMA transfer exceeding a page frame. Further, when the capacity of the main memory is large, a DMA device without the ability to access all the main memory areas cannot perform the DMA transfer.

In order to solve these problems, there is a method of connecting a DMA device to a logical address bus and accessing a main memory with a logical address. However, in this method, the coupling between the CPU and the memory management unit becomes loose, and the access performance of the CPU to the main memory is reduced.

Some microprocessors have a memory management unit built into a CPU chip to improve memory access performance, but in that case, a DMA device cannot be connected to a logical address bus.

On the other hand, as shown in FIG. 8, in a memory management unit of a system for performing mapping by searching for an address conversion table 8 in a main memory (not shown), if a search for the address conversion table 8 occurs frequently, The transfer capability of the logical address bus is reduced, and it is not possible to connect a DMA device that requires real-time performance.

Therefore, apart from a memory management unit having an address conversion table for converting a logical address generated by a CPU into a physical address, a DMA address conversion table for mapping a DMA address output from a DMA device to a physical address is stored. Some of the above-mentioned problems can be solved by providing a memory to be used.

[0008] This DMA address conversion table has a CPU
And is mapped to a part of the physical address, and the CPU can read / write by accessing the physical address. This DMA control method is disclosed in JP-A-63-245545.

From a certain logical address (start address),
A processing operation in a case where an area of a certain size (total transfer size) is divided into a certain transfer size (unit transfer size) and DMA-transferred will be described with reference to FIGS. To simplify the description, the page size and the total transfer size are assumed to be multiples of the unit transfer size.

When performing the above-mentioned DMA transfer, the start address is substituted for the current logical address and the total transfer size is substituted for the transfer size (step S21 in FIG. 9), and the quotient obtained by dividing the current logical address by the page size is used for the page number. , And substitute the remainders for the offsets (step S2 in FIG. 9).
2).

Subsequently, a base address corresponding to the page number is obtained as a page address by referring to the address conversion table 8 (step S23 in FIG. 9). A value obtained by adding an offset to the page address (base address) is substituted for the current physical address (step S2 in FIG. 9).
4) DMA transfer the data of the unit transfer size to the current physical address (step S2 in FIG. 9).
5).

Thereafter, a value obtained by subtracting the unit transfer size from the remaining transfer size is substituted for the remaining transfer size (step S26 in FIG. 9), and it is determined whether or not the remaining transfer size is “0” (step S27 in FIG. 9). .

If the remaining transfer size is not "0", a value obtained by adding the unit transfer size to the offset is substituted for the offset (step S28 in FIG. 9), and it is determined whether or not this offset is equal to the page size (FIG. 9). 9 steps S2
9). If the remaining transfer size is "0", the process is terminated.

When the offset is equal to the page size, that is, when the DMA transfer of the current page is completed, the page number is incremented (+1), "0" is substituted for the offset (FIG. 9, step S29), and the routine proceeds to step S23. Note that if the offset is not equal to the page size,
Move to step S24.

[0015]

SUMMARY OF THE INVENTION The above-described conventional DMA
In the control method, even when performing a DMA that crosses a page boundary between consecutive pages on a physical address, the original D
Since a base address read cycle not directly related to the MA transfer is always executed, it takes the same time as in the case of performing DMA between discontinuous pages on a physical address.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to perform a DMA control capable of performing a high-speed DMA transfer when performing a DMA that crosses a page boundary between consecutive pages on a physical address. An object of the present invention is to provide a device, a control method thereof, and a recording medium on which a control program is recorded.

[0017]

A DMA controller according to the present invention performs direct memory access to a plurality of pages in a main memory, and includes a base address of each page of the main memory and a corresponding page. An address conversion table that stores information relating to the continuity of the pages in association with each other; a determination unit that determines whether there is a continuous page following the page accessed at the time of the direct memory access based on the address conversion table; Generating means for generating a base address of the next page when it is determined that there is a continuous page.

A DMA control method according to the present invention is a DMA control method for performing a direct memory access to a plurality of pages on a main memory, wherein the presence or absence of a continuous page following the page accessed at the time of the direct memory access is determined by the main memory. A step of determining based on the information on the continuity of the page stored in association with the base address of each page, and a step of generating a base address of the next page when it is determined that there is a continuous page in this determination. It has.

A recording medium on which a DMA control program according to the present invention is recorded is a recording medium on which a DMA control program for performing direct memory access to a plurality of pages on a main memory is recorded, wherein the DMA control program is the direct memory. The control means for controlling access determines whether or not there is a continuous page following the page to be accessed at the time of the direct memory access based on information on continuity of the page stored in association with the base address of each page of the main memory. The base address of the next page is generated when it is determined that there is the continuous page.

That is, in the DMA control method of the present invention,
Corresponding to each page stored in the address conversion table, the number of pages that are continuous in the forward direction on the physical address of the page is stored.

By referring to the number of pages that are continuous with each page, it is possible to determine whether the page is continuous with another page on a physical address. When performing a DMA that crosses a page boundary between the current pages, it is possible to avoid executing a base address read cycle that is not directly related to the original DMA transfer. Therefore, the DM exceeding the page boundary between the pages that are continuous on the physical address
When performing A, high-speed DMA transfer can be performed.

[0022]

Next, an embodiment of the present invention will be described with reference to the drawings. FIGS. 1 and 2 are flowcharts showing a DMA transfer processing operation according to an embodiment of the present invention, and FIG. 3 is a diagram showing a configuration of an address conversion table according to an embodiment of the present invention. In FIG. 3, the address conversion table 1 stores a base address 1a and a continuous page number 1b corresponding to each other.

Here, a DMA (Direct Mem) is stored in a plurality of pages (of the same size) on a main memory (not shown).
transfer data is mapped, a page number (natural number) is assigned to each page in ascending order of the base address 1a, and a list of base addresses 1a of each page is stored in the address conversion table 1. I have. The number of continuous pages 1b indicates the number of pages that are continuous in the forward direction on the physical address for each page.

FIG. 4 is a block diagram showing a system configuration according to an embodiment of the present invention. In the figure, an information processing system according to one embodiment of the present invention has a CPU (Central Processing Unit) 2
, A bridge 3, a main memory 4, a DMA controller 5, and a DMA data transfer source / destination 6. The CPU 2 and the main memory 4 communicate with the DMA controller 5 and the DMA controller 5 via the bridge 3 and the bus 100. It is connected to the data transfer source / destination 6.

FIG. 5 is a block diagram showing the configuration of the DMA controller 5 of FIG. In the figure, the DMA controller 5 includes a sequencer 51, arithmetic units 52, and a register 53.

FIG. 6 is a diagram showing a memory map according to one embodiment of the present invention. In the figure, DMA transfer data is mapped on the main memory 4 into five pages (pages 0 to 4). In this case, pages 1 to 3 are continuous on the physical address, and the number of continuous pages of each of pages 0 to 4 is 0, 2, 1, 0, 0, respectively.

Also, pages 0 to 4 are stored in the main memory 4.
In addition, an address conversion table 1 that holds a list of a base address 1a and a continuous page 1b of each page is stored, and the page size is 4 kbytes. The processing operation of the DMA transfer according to one embodiment of the present invention will be described with reference to FIGS. 1 and 2 are realized by the DMA controller 5 executing a program recorded in a control memory (not shown).
The control memory may be a floppy disk, a ROM (Read Only Memory), or the like.

First, the DMA flow will be described with reference to FIGS. Here, an area of a certain size (total transfer size) is divided into a certain transfer size (unit transfer size) from a certain logical address (start address),
The processing operation when the A transfer is performed will be described. To simplify the description, the page size and the total transfer size are assumed to be multiples of the unit transfer size.

When performing the above-described DMA transfer, the start address is substituted for the current logical address and the total transfer size is substituted for the transfer size (step S1 in FIG. 1), and the quotient obtained by dividing the current logical address by the page size is used for the page number. , And substitute the remainders for the offsets (step S in FIG. 1).
2).

Subsequently, referring to the address conversion table 1, the base address corresponding to the page number on the address conversion table 1 is set as the page address, and the continuous page number corresponding to the page number on the address conversion table 1 is set as the continuous page number. (Step S3 in FIG. 1).

A value obtained by adding an offset to the page address (base address) is substituted for the current physical address (step S4 in FIG. 1), and data of a unit transfer size is DMA-transferred to the current physical address (FIG. 1). Step S5).

Thereafter, a value obtained by subtracting the unit transfer size from the remaining transfer size is substituted for the remaining transfer size (step S6 in FIG. 1), and it is determined whether or not the remaining transfer size is "0" (step S7 in FIG. 1). . If the remaining transfer size is “0”, the above-described DMA transfer processing is terminated.

If the remaining transfer size is not "0", a value obtained by adding the unit transfer size to the offset is substituted for the offset (step S8 in FIG. 2), and it is determined whether or not this offset is equal to the page size (FIG. 2). Two steps S9).
If the offset is not equal to the page size, the process moves to step S4.

When the offset is equal to the page size, that is, when the DMA transfer of the current page is completed, the page number is incremented (+1) and "0" is substituted for the offset (step S9 in FIG. 2).

If the number of continuous pages is "0" (step S11 in FIG. 2), the process proceeds to step S3. Also,
If the number of continuous pages is not "0" (FIG. 2, step S1)
1) The value obtained by adding the page address to the base address is substituted for the base address, the number of continuous pages is decremented (-1) (step S12 in FIG. 2), and the process proceeds to step S4.

Next, with reference to FIG. 1, FIG. 2, and FIG. 6, the processing operation of the DMA transfer according to one embodiment of the present invention will be specifically described. Here, under the state of the memory map shown in FIG. 6, when the unit transfer size is 32 bytes, the area of 2 kbytes from the logical address “1C00h”, that is, the area of the logical addresses “1C00h” to “23FFh” is DMA-transferred. Will be described below.

First, the start address “1C00h” is set as the current logical address, and the total transfer size “20” is set as the transfer size.
48 (= 2k) bytes "(step S in FIG. 1).
1) The quotient “1 (= 1C00h / 1000h)” obtained by dividing the current logical address by the page size is used as the page number,
The remainder “C00h (= 1C00h% 1000h)” is substituted for the offset (step S2 in FIG. 1).

Subsequently, by referring to the address conversion table 1, the base address "1A000h" corresponding to the page number "1" on the address conversion table 1 is set as the page address and the page number "1" on the address conversion table 1 is set. The corresponding continuous page number "2" is obtained as the continuous page number (step S3 in FIG. 1).

The value obtained by adding an offset to this page address (base address) is "1AC00h (= 1A00
0h + C00h) "is substituted for the current physical address (step S4 in FIG. 1), and the current physical address" 1 "
DMA transfer of data of the unit transfer size, that is, data of 32 bytes, is performed for "AC00h" (step S5 in FIG. 1).

Thereafter, "2016 (= 2048-32) bytes" obtained by subtracting the unit transfer size from the remaining transfer size is substituted for the remaining transfer size (step S6 in FIG. 1), and whether or not the remaining transfer size is "0" Is determined (step S7 in FIG. 1).

In this case, since the remaining transfer size is not “0”, the value obtained by adding the unit transfer size to the offset “C2
0h (= C00h + 32) "is substituted for the offset (step S8 in FIG. 2), and it is determined whether or not this offset is equal to the page size (step S9 in FIG. 2).

As a result, since the offset “C20h” is not equal to the page size “1000h”, the step S
4 and the offset is changed to the page size “1”.
000h ".

The offset is page size "1000h"
When the DMA transfer of the current page is completed, "2 (= 1 + 1)" is substituted for the page number and "0h" is substituted for the offset (step S in FIG. 2).
9).

Here, since the number of continuous pages corresponding to page number "2" is "1" (step S11 in FIG. 2), the sum of the base address and the page address "1B00"
0h (= 1A000h + 1000h) "is substituted for the base address, and" 1 (= 2-1) "is substituted for the number of continuous pages (step S12 in FIG. 2), and the process proceeds to step S4.

The above processing is repeated until the remaining transfer size becomes "0", and when the remaining transfer size becomes "0",
The above-described DMA transfer processing ends.

FIG. 7 is a block diagram showing another system configuration of one embodiment of the present invention. 7, the configuration is the same as that of the information processing system shown in FIG. 4 except that the DMA controller 5 and the DMA data transfer source / destination 6 shown in FIG. 4 are mounted on the same device 7, and the operation thereof is also described above. As you did.

As described above, the base address read cycle at the page boundary portion of the main memory 4 can be avoided based on the continuous page number information stored in the address conversion table 1, and the time required for the entire DMA transfer can be shortened. Therefore, when performing DMA beyond the page boundary between consecutive pages on the physical address, the DMA transfer can be performed at a higher speed than the conventional method.

It should be noted that the address conversion table 1 requires an extra storage area by an amount corresponding to the increase in the storage portion of the number of continuous pages as compared with the conventional address conversion table 8 shown in FIG.
Although the number of steps in the DMA transfer processing according to the embodiment of the present invention is larger than that in the conventional DMA transfer processing, the time required for the entire DMA transfer is not longer.

This is because in the currently used DMA transfer processing, the value of the base address of each page is generally not a byte unit but a larger byte value, and therefore, the lower byte of the kernel base address is used. Bits are not used, and it is sufficient to store the continuous page number data in the unused bit portions.If such continuous page number data is stored, the continuous page number data is simultaneously read during the base address read cycle. Because you can.

[0050]

As described above, according to the present invention, in a DMA control device for performing direct memory access to a plurality of pages in a main memory, the base address of each page in the main memory and the continuity of the page. Based on an address conversion table that stores information in association with information, it is determined whether there is a continuous page following the page to be accessed at the time of direct memory access, and when it is determined that there is a continuous page, a base address of the next page is generated. In addition, there is an effect that high-speed DMA transfer can be performed when performing DMA beyond a page boundary between consecutive pages on a physical address.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a DMA transfer processing operation according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a DMA transfer processing operation according to an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of an address conversion table according to one embodiment of the present invention.

FIG. 4 is a block diagram illustrating a system configuration according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a DMA controller of FIG. 4;

FIG. 6 is a diagram illustrating a memory map according to an embodiment of the present invention.

FIG. 7 is a block diagram showing another system configuration according to an embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of an address conversion table according to a conventional example.

FIG. 9 is a flowchart showing a DMA transfer processing operation according to a conventional example.

[Explanation of symbols]

 1 Address Conversion Table 1a Base Address 1b Number of Consecutive Pages 2 CPU 3 Bridge 4 Main Memory 5 DMA Controller 6 DMA Data Transfer Source / Destination 7 Device

Claims (9)

[Claims] 1. A DMA control device for performing direct memory access to a plurality of pages on a main memory, wherein a base address of each page of the main memory and information on continuity of the page are stored in association with each other. An address conversion table, determining means for determining the presence or absence of a continuous page following the page to be accessed at the time of the direct memory access based on the contents of the address conversion table, and a next page when the determining means determines that the continuous page is present. And a generating means for generating a base address of the DMA controller. 2. The DMA controller according to claim 1, wherein the information on the continuity of the page is the number of pages that are consecutive in the forward direction on the physical address of the page. 3. The apparatus according to claim 1, wherein said generating means is configured to generate a base address of the next page from a base address and a page size of a page accessed at the time of the direct memory access. The DMA controller according to any one of the preceding claims. 4. A DMA control method for performing a direct memory access to a plurality of pages on a main memory, wherein a presence or absence of a continuous page following a page accessed at the time of the direct memory access is determined by a base address of each page of the main memory. And a step of generating a base address of a next page when it is determined that there is a continuous page in this determination. DMA control method. 5. The DMA control method according to claim 4, wherein the information on the continuity of the page is the number of pages that are continuous in the forward direction on the physical address of the page. 6. The step of generating a base address of the next page, wherein the base address of the next page is generated from a base address and a page size of a page to be accessed at the time of the direct memory access. A DMA control method according to claim 4 or claim 5. 7. A recording medium on which a DMA control program for performing direct memory access to a plurality of pages on a main memory is recorded, wherein the DMA control program includes: a control unit for controlling the direct memory access; The presence or absence of a continuous page following the page to be accessed at the time of access is determined based on the information on the continuity of the page stored in association with the base address of each page in the main memory. A recording medium on which a DMA control program is recorded, wherein a base address of a next page is generated when the program is executed. 8. The recording medium according to claim 7, wherein the information on the continuity of the page is the number of pages that are consecutive in the forward direction on the physical address of the page. . 9. The program according to claim 1, wherein the DMA control program causes the control means to generate a base address of the next page from a base address and a page size of a page to be accessed at the time of the direct memory access. A recording medium on which the DMA control program according to claim 7 or 8 is recorded.