JPS63255750A - Memory system - Google Patents

Abstract

PURPOSE:To realize an efficient and large-capacity memory system while keeping the software compatibility with a conventional extended memory by adding a map register, in which mapping information including set information supplied from a CPU is stored, to the memory system. CONSTITUTION:Arbitrary data (D0-D7) is written from a CPU (omitted in the figure) to a page control register 220. Simultaneously, a page selecting signal and a set selecting signal are generated in accordance with the address (A0-A15) from the CPU by a read/write control circuit 200, and data D7-D0 and the set selecting signal are written in a map register 250 selected by the page selecting signal. When the memory access to a page frame is performed by the CPU, the map register corresponding to a physical page is selected by each signal and a memory chip 280 is accessed in accordance with the address generated in an address synthesizing circuit 260 by the signal outputted from this register and said address A0-A13.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION (Field of Industrial Application) The present invention relates to a LIM type memory system, which is one of the extended memory types.

(Prior Art) In recent years, the memory capacity of personal computers has tended to increase, and various types of memory systems have been proposed. LIX type expansion memory is a type of expansion memory.
This method uses a part of the CPU's memory address space as a window, and accesses up to 8MB of expanded memory through the window. LIM is the United States Lotus/Intel/Mi
This is a method in which the three companies of Crosoft jointly announced the specifications, and an example of a product is the Above board from 1nte1 in the United States.

FIG. 5 shows the memory relationship. The extended memory window is l1
There are four consecutive 3KB units. The 18KB window is called a physical page, and the four physical pages together are called a page frame. Further, the extended memory accessed from each physical page is also in units of 16 KB and is called a logical page. There are a maximum of 512 logical pages, and the capacity of one page is 16KB x 5.
It becomes 12-8MB. The correspondence between physical pages and logical pages is done by the CPU by changing the contents of an I/O port called a page control register, and CPt1 can access up to 8MB of extended memory in total. A system block diagram is shown.

Each expansion memory 4/O to 440 has a set number, and each page control register 411 to 441 has a set number.
/O port address is supported. There are four page control registers 411-441 in each extended memory 4/O-440. Physical page Y1 set X (X-0,1,
5,8Y-0,1,2,3) page control registers are:
It has the format shown in Figure 7. In the figure, each bit has the following meaning.

PE: Page Enable Bit 0: Disabled Mapping of physical page Y to logical pages is not performed within the range of logical pages of set X.

1; Mapping of enabled physical page Y to logical page is performed within the range of logical pages of set X.

PAi: Bit in page address Specifies the logical page to which physical page Y is mapped. PE-
When it is 0, it is invalid.

Next, to explain the operation, CPUll0 connects the standard $ (Convcntoin) via the system bus 120.
al) Memory 130, Extended memory 140, Extended (EXI) andcd) Memory 4 0 to 4
40 respectively.

When accessing extended memory 4/O to 440, set any value 17 to page control registers 41 to 441 in advance.
Set by 0 write.

Now, assume that physical page Y is mapped to logical page Z. Kokote, Y-0,1,2,3,Z-0,1,-,5
It becomes 12. First, determine which set X logical page Z is on. Here, it is assumed that X-0, 1, 5, and 6.

Next, determine the offset of logical page Z within the logical page range of set X. Set this offset to PAi
CPt1 is the page control register 411-44 of page Y1 set X.
Write I/O to 1. At the same time, page Y of another set
The page control registers 411 to 441 of
I/O write the 8-bit data. Note that PAl at this time is arbitrary. Page control register 411
After setting data to ~441, when CPt1LIO performs memory access to physical page Y, only set X, which is PE-1, is selected among page control registers 411~441, and 443
Among them, memory access is performed to the corresponding memory chip.

(Problem to be Solved by the Invention) Advances in semiconductor technology have made it possible to use highly integrated memory chips, and the four expansion memory boards 4/O to 440 in FIG. It has become possible to create. In this case, the conventional system in which the expansion memory circuit is quadruple as it is has the disadvantage that the control circuit becomes complicated and the cost also increases.

Another possible method is to increase the bit length of the PA of the page control registers 411 to 441 from 7 bits to 9 bits, and control all 512 logical pages with one page control register. However, in this method, the page control register seen from the software is different from the conventional method, and there is a problem with software compatibility.

The present invention has been made based on the above drawbacks, and by introducing a new concept of mapped registers, it provides a highly efficient and large capacity memory system while maintaining software compatibility with conventional extended memory. The purpose is to

[Configuration of the Invention] (Means for Solving the Problems) The memory system of the present invention has a configuration that achieves high efficiency and large capacity while maintaining software compatibility with conventional expansion memories. For this reason, conventionally, this type of device has a page control register, a read/write control circuit, a decoding circuit, an address synthesis circuit, a memory control circuit, and a memory chip with a map that stores mapping information including set information supplied from CPt1. A register is added.

(Operation) In the above configuration, the page control register stores mapping information within a set. The map register stores mapping information including set information. The read/write control circuit controls I/O reads and writes to the page control register and I/O writes to the map register. The decode circuit determines the physical frame number within the page frame address. The address synthesis circuit synthesizes a memory access address using the mapping information in the map register as the upper address and the lower address of the system bus contention address as the lower address. The memory control circuit handles memory access addresses and memory read/
Memory access is performed according to the write signal, memory access permission signal, and page frame decode signal. Data is input and output to and from the memory chip according to a memory control signal and a memory chip address.

This makes it possible to realize a highly efficient, large-capacity memory system while maintaining software compatibility with conventional expanded memory.

(Example) An example of the present invention will be described below with reference to the drawings. FIG. 1 is a system block diagram illustrating one embodiment of the present invention. In the figure, 1/O is the CPU, 1
20 is a system bus.

130 is a standard memory. Standard memory 130 includes a memory control circuit 131 and a memory chip 131, and is connected to cputto via system bus 120. 140 is an expansion memory. The expansion memory 140 is composed of a memory control circuit 141 and a memory chip 142, and is connected to cputto via the system bus 120. 150 is a memory system. The memory system 150 is composed of a page control register 151, a map register 152, a memory control circuit 153, and a memory chip 154.
Connected to t+tio. The page control register 150 includes the page control registers 411, 421, 431, and
It has the same format as 441, and 1 like the system in Figure 6.
There are 6 of them. There are four map registers 152 corresponding to four physical pages, and each map register has a tobt
It is t long. The map register for page Y (Y-0, 1, 2, 3) has the format shown in FIG.

In the figure, each bit has the following meaning.

ME: map enable bit 0; disabled Mapping of physical page Y to a logical page is not performed in the memory system of FIG.

1; The mapping of an enabled physical page Y to a logical page is performed in the memory system shown in FIG.

MAl: Map address bits (1-0 to 8) Specify the logical page to which the physical page is mapped. It is invalid when HE-0.

In the case of ME-0, the memory system is not used at all, or it is used for a mixed configuration with conventional expansion memory. Furthermore, the map register 152 is not directly visible from CPUll0, but a total of 16 page control registers are visible as before. Writing to map register +52 is performed simultaneously with writing to register 151 (I/O write) under page control by CPUll0.

Now, the data shown in FIG. 7 is I/O written to the page control register of page Y/set X by CPUIIO, and thereafter, the data is read by I/O read by CPUIIO. On the other hand, the data shown in FIG. 4 is written into the corresponding map register of the map registers 152 by I/O write.

That is, the same contents as the PE bit are written to the ME bit, and the set number and logical page number are represented by the 9-bit HA bit.

FIG. 2 shows a block diagram of a memory system that is an embodiment of the present invention. In the figure, 121 is a data bus, 122 is an address bus, and CPt11/O
and the memory system 150. 2/O is a read/write control circuit, and is connected to the address bus 122 via signal lines 211 and 212. 220
is a page control register, which is connected to the data bus 121 via a signal line 221 and to the read/write control circuit 2/O via a signal line 213. 2
30 is a decoding circuit, which is connected to the address bus 122 via a signal line 231. 240 is a decoding circuit, which is connected to the decoding circuit 230 via a signal line 232 and to the address bus 122 via a signal line 233. 250 is a map register, and a signal line 25L252 is connected to the read/write control circuit 2/O via signal lines 214 and 215.
to the data bus 121 via a signal line 241
is connected to the decoder 240 via. 260 is an address synthesis circuit, which is connected to the address bus 122 via a signal line 261 and to the map register 250 via a signal line 253. 270 is a memory control circuit that connects the map register 250 via a signal line 254, the address bus 122 via a signal line 271, the decoder 230 via a signal line 232, and the signal line 262. and is connected to the address synthesis circuit 260. 280 is memory
The chip is connected to the memory control circuit 270 via signal lines 272 and 273 and to the data bus 121 via signal lines 28.

The operation of the embodiment of the present invention will be described in detail below.

cputio inputs/inputs arbitrary data (Do to D7) to the page control register 220 via the signal line 221.
Write by O write. At the same time, the read/write control circuit 2/O receives signal line 211 from CPUll0.
According to the control signal supplied via the signal line 21
A page selection signal and a set selection signal are generated from the addresses (AO to A15) supplied via 1. Of the map register 250, the read/write control circuit 2
The map register selected by the page selection signal supplied from /O via signal line
The data (D7) supplied via the signal line 251
) and the data (D6
~DO), and a set selection signal (B
A8 and BA7) are written. When CPtJllo performs a memory access to a page frame, the map register corresponding to the specified physical page is selected by each signal.

Further, the address synthesis circuit 260
50 via the signal line 253 (H
A memory access address is generated by combining A) and the lower address (AO to A13) supplied from CPUll0 via the signal line 251. The memory control circuit 270 then sends a memory chip address to the memory chip 280 via a signal line 272 and a memory chip address via a signal line 273 in accordance with the memory access address supplied from the address synthesis circuit 260. By supplying control signals, memory read, memory
Do light. Memory φ access address is 23b
It can support 8MB memory chips. This corresponds to 512 logical pages. CPtJ
By changing the data written to page control register 220, llo can simultaneously change the data in the map register.

In other words, it is possible to permit/prohibit access to the memory chip 280 and change the memory address.

Note that in this embodiment, the page frame address is fixed. Like Intel1's AbOVe board, it can also be applied to a system in which the page frame address is variable. Further, in this embodiment, the explanation has been given of an expansion memory in which four conventional expansion memories are combined into one, but the present invention can also be applied to an expansion memory in which two or three conventional expansion memories are combined into one. In that case, two or three sets of page control registers would be prepared.

In this way, one expansion memory board can handle up to 51
Can support two logical pages. It is not necessary to have a memory control circuit for each set, and only one memory control circuit is sufficient. There is no need to read the data in the page control register by the CPU when accessing the memory, and the memory access address can be determined before the PE is read, which reduces the speed required of the memory control circuit. In terms of software, it is compatible with conventional expansion memory, and can be mixed with conventional expansion memory. Even if the number of memory chips mounted on the board is small and the capacity is small,
It is easy to expand by simply adding memory chips, so 8MB/board can be achieved.

[Effects of the Invention] As explained above, there is an effect that an extended memory of up to 8 MB can be realized while maintaining software compatibility with conventional extended memory.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing the format of the map register shown in FIG. Figure 4 shows the relationship between the upper two digits of the map register shown in Figure 1 and the set number, Figure 5 shows the relationship between memory, and Figure 6 shows the relationship between the memory.
The figure shows a conventional example, and FIG. 7 shows the format of the page control register shown in FIG. 6. 2/O...Read/write control circuit 220...Page control register 230.240...Decode circuit 250...Map register 260...Address synthesis circuit 270...Memory control circuit 280...・Memory chip

Claims (1)

[Claims] Defining a part of the address space of the CPU as a window,
In an information processing device that accesses expanded memory to which set numbers are assigned to each of a group of memory blocks to which page numbers are assigned through this window, pages of memory blocks in which data supplied from the CPU are stored are stored. A page control register stores mapping information that is information representing a number, and a page control register that stores mapping information that is information representing a number, and mapping information that stores data supplied from the CPU and sets information that represents the set number of the extended memory that includes the memory block in which the data is stored. Maps to be stored
a read/write control circuit that controls I/O write to the page control register, I/O read, and I/O write to the map register according to a control signal supplied from the CPU; a decoding circuit that detects a page frame address from a memory address and obtains a physical page number; and a system that sets the mapping information supplied from the map register to an upper address of the memory access address and is supplied from the CPU.・Set the memory address as the lower address of the memory access address.
an address synthesis circuit for synthesizing access addresses; a memory access permission signal supplied from the map register; a page frame decode signal supplied from the decode circuit; and a memory access signal supplied from the address synthesis circuit.・According to the address and memory read/write signals supplied from the CPU, the memory
A memory system comprising: a memory control circuit that performs access; and a memory chip that inputs and outputs data in accordance with a memory control signal and a memory chip address supplied from the memory control circuit.