JPH01269141A - Microprocessor having extension port - Google Patents

Abstract

PURPOSE:To extend an input output port at the time of necessity without providing an exclusive-use extending terminal group by using a special input port extending means when the instruction to require an address, which a data input output means does not possess, from a program storing means. CONSTITUTION:When the instruction to require an address, which a data input output means does not possess, is sent from a program storing means 1, an input output port extending means 14 to send extending address data from the port of the special address of the data input output means and continuously, give and receive the data with the storing means of external data through the same port is provided. Namely, a second address register 9 holds the addresses of a RAM (including stack area) 12, a general purpose parallel input output port 13 and an input output port 14 for extending. Thus, the exclusive-use extending terminal group is not provided, and a microprocessor, the input output port can be extended only at the tie of the necessity, can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the configuration of input/output ports of microprocessors.

BACKGROUND OF THE INVENTION In recent years, software programming type microprocessors have been widely used in various fields, and their configuration includes a program storage means for storing a program consisting of a group of instructions to be executed sequentially, and a plurality of addresses. A data input/output means whose address is specified by an instruction stored in a program storage means; Some configurations include a data bus that connects the output port (corresponding to the output port) and the calculation means.

Further, a typical configuration thereof is shown in Japanese Patent Publication No. 5B-33584.

Such software programming type microprocessors can be used for a variety of purposes, so the program size and the number of required input/output ports usually vary greatly depending on the purpose. Furthermore, in most one-chip microprocessors, the program storage area is comprised of read-only memory (hereinafter abbreviated as ROM), and the storage area for constantly changing data is readable/writable memory (hereinafter abbreviated as RAM). ). Therefore, many one-chip microprocessors form microprocessor families consisting of package groups with various ROM sizes, RAM sizes, and several types with different numbers of terminals in order to flexibly accommodate various specifications. ing.

The existence of many families due to differences in memory size and number of input/output terminals is not desirable from the standpoint of standardization. One way to expand and utilize the limited number of input/output terminals is to use the microprocessor's data bus itself as a group of input/output terminals, as seen in many multi-chip microprocessors such as Intel's 8080 and 8086. A method is used in which an input/output port is configured externally, or a specific input/output port is assigned to data communication with an expander connected externally.

Problems to be Solved by the Invention However, in the above-mentioned conventional method, the former method consists of a microprocessor system including an input/output board as a single I/O board.
The latter method cannot be implemented with C chips and is uneconomical for small-scale systems; the latter method is suitable for small-scale systems that do not require expansion of the input/output ports when implemented by hardware. For this system, a group of expansion terminals for connecting to an external expander becomes a useless piece of equipment, and if this is implemented using software, it not only increases the burden on the programmer, but also requires a lot of processing time. There is a problem that it takes time to
Was.

In view of this, an object of the present invention is to provide a microprocessor having an expansion board that allows input/output ports to be expanded only when necessary, without providing a dedicated expansion terminal group.

Means for Solving the Problems In order to solve the above-mentioned problems, a microprocessor having an extended host according to the present invention provides that when an instruction is sent from the program storage means to request an address not owned by the data input/output means, the microprocessor according to the present invention The configuration includes input/output port expansion means for transmitting extended address data from a port at a specific address of the data input/output means, and then transmitting and receiving data to and from an external data storage means via the same port. It's happening.

According to the above-described configuration, the present invention transfers the boat of a specific address of the data input/output means to the extended boat only when an instruction is sent from the program storage means to request an address not owned by the data input/output means. Otherwise, the port at a specific address of the data input/output means functions as a normal input/output port.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a microprocessor having an expansion board in one embodiment of the present invention. In FIG. 1, an instruction selected by a program pull counter 2 from an instruction ROM 1 in which a program consisting of a group of sequentially executed instructions is stored is sent to an instruction queue 3 for holding and pre-reading instructions. The instruction once held in the instruction queue 3 is sent to the instruction decoder 4, and its address index section is sent to the address bus 6.
sent to. A group of control signals produced by the instruction decoder 4 are supplied to each block constituting the microprocessor via a control bus e. Further, a plurality of timing signals for processing by the microprocessor are generated in the timing generator, and these timing signals are supplied to each block via the control bus 6. Address bus 6 and programmable counter 2. First address register8. Second address register9. The data buses 10 are connected to each other so as to send address data to each other. The first address register 8 holds the memory address of the tape/L/ROM 11, and the second address register 9 holds the memory address of the RAM (including the stack area) 12° general-purpose parallel input/output port 13.
Holds the address of the expansion input/output boat 14. Also,
The MSB (most significant bit) of the address data output from the first address register 8 is applied to the synchronization signal generator 16, and the output signal of the synchronization signal generator 15 is used for externally connected expanders and memories. It is output as a synchronization signal to the synchronization output terminal SS. General purpose parallel input/output capo-1
, (PIO) 13, each of the three groups of input/output lines is Ao-
The input/output lines of the expansion input/output board (EXP) 14 are connected to the input/output terminals of the A, B, and C groups, which are composed of the A16 terminal, BO to B1s terminals, and CO to C16 terminals, and the input/output lines of the expansion input/output board (EXP) 14 are also connected to the input/output terminals of the B group. connected to the terminal. Furthermore, the data bus 1o has a first register 16 and a second register 17.
The input section of an ALU (arithmetic and logic unit) 18 is connected through the ALU 8, and the output of the ALU 8 is supplied to an accumulator unit (including a group of flags) 19. There is also a bidirectional connection between the accumulator unit 19 and the data bus 1o. connected by buses.

It is assumed that the data output section of each of the circuits d and ri has a three-state configuration, and is maintained in a high impedance state during a period when data output is not required. In addition, including the expansion input/output board 14 and the synchronization signal generator 15,
It is assumed that necessary timing signals and control signals are supplied to each block via the control bus 6.

Regarding the microprocessor configured as above,
The operation will be explained with reference to the block diagram shown in FIG. 1, the timing chart of the main parts shown in FIG. 2, and the memory map shown in FIG. 3.

First, FIGS. 2A, B, and C each show the signal waveform of the basic timing signal output from the timing chart i7 based on the clock signal waveform supplied to the external clock input terminal 20 of FIG. This is the second diagram,
E indicates the signal waveform of the synchronization signal output from the synchronization signal generator 16 when the extended address is selected by the second address register 9.
FIG. F is a signal waveform showing the active period of address information and data information exchanged via the Co-Cl3 terminal. The synchronization signal shown in Figure 2 is output when writing data to an external memory or expander, and the synchronization signal shown in Figure 2E is output when reading data from an external memory or expander. Output.

Next, Figure 3 shows tape/L/ROM11, RAM1
2. This shows the memory map of the general-purpose parallel input/output board 13 and the external expansion input/output unit, and the address bus 6.
Of the 10-bit addresses supplied to the first address register 8 and the second address register 9, 612 words from address 000 to address (IFF) are used as the table ROM area; 266 words from address (2FF) to address (2FF) are used as the internal I0 area, and 266 words from address (300> to (3FF)) are used as the external process 0 area. Also, the internal IO area includes RAM12, A general-purpose parallel input/output boat 13 is mapped, and in particular,
The general-purpose parallel input/output port 1 is located at address (2F F).
It is assumed that the input/output units of group C in No. 3 are mapped.

Now, in the microprocessor shown in Fig. 1, the instruction RO
When a data transfer instruction for accessing the external IO area in FIG. 3 is extracted from M1, the address index portion of the instruction is supplied to the second address register 9 via the instruction queue 3.

Further, an identification signal indicating whether the command is a write command to the external IO area or a read command from the external IO area is sent to the synchronization signal generator 15 via the command decoder 4.
is supplied to the third address register 9 by the second address register 9;
When the external xO area address in the figure is selected, the RA
The M12 and the output section of the general-purpose parallel input/output board 13 are both in a high impedance state, and conversely, the expansion input/output port 14 and the synchronization signal generator 16 are in an operating state.

In this state, when a write command to the external IO area is executed, first, at the timing shown in FIG. The address information of Co-07
A "1" level is output from the C15 terminal as a write enable signal to an externally connected expander or memory. Next, the second
At the timing b in Figure F, the information on the data bus 1o is C.

- Output from the C15 terminal. It is assumed that the expansion input/output port 14 has a data latch that holds the information on the data bus 10 at that time for at least the period b in FIG. 2. During this time, the synchronization signal shown in the second diagram is output from the SS terminal. Therefore, at the leading edge of the synchronization signal in the second diagram, the externally connected expander or memory receives the address of the external IO area output from the CO to C7 terminals and the write address output from the C15 terminal. can recognize the enable signal,
At its trailing edge, Co-07
Data output from the terminal can be read.

Next, when a read instruction from the external IO area is executed, 8-bit address information is output from the CO to C end terminals at timing a in Figure 2 F, and the C15 terminal is connected to the outside. A 0" level is output as a write disable signal for the expander or memory. The synchronization signal shown in Fig. 2E is output from the SS terminal.
At the leading edge, the address of the external IO area output from the Co-07 terminal and the write enable signal output from the C16 terminal can be recognized, and the period from the trailing edge to the trailing edge of the clock signal can be recognized. That is, during the period b in FIG. 2F, data is output from an externally connected expander or memory.

On the other hand, when a data transfer instruction for accessing the internal work area shown in FIG. 3 is retrieved from the instruction ROM1, the RA
M12 and the general-purpose parallel input/output port 13 are not in operation, and conversely, the expansion input/output port 14 and the synchronization signal generator 1
6 becomes inactive, and the Co-015 terminal is assigned to the general-purpose parallel input/output port 13.

In this way, in the microprocessor shown in FIG. 1, the data input/output terminal group Go-C1s of the general-purpose parallel input/output board 13 can also be used as a data input/output terminal group for expansion of the external IO area. The input/output board or memory area can be expanded by adding a minimum number of terminals.

By the way, as already explained, with the microprocessor of the present invention, not only can an expander be connected to the outside to expand the number of ports, but also the ROM area and RAM area can be easily expanded. Another embodiment of the present invention shown in FIG. 4 is based on the 16-bit address information supplied from the address bus 6 to the address register 20.
If it is within the range up to the address, access the internal memory or IO boat, and then access (0400> from the address (7FFF)
If the range is up to the address, the expansion input/output port 14 and the synchronization signal generator 16 are operated to access the externally connected memory. Therefore, the memory map of the microprocessor shown in FIG. 4 becomes as shown in FIG.

Effects of the Invention As is clear from the above description, the microprocessor with an expansion port of the present invention has a program storage means for storing a program consisting of a group of instructions to be executed sequentially, and a plurality of addresses, and the address A data input/output means specified by an instruction stored in the storage means, an arithmetic means that executes a data operation based on an instruction sent from the program storage means, and a connection between the data input/output means and the arithmetic means. When an instruction is sent from the data bus and program storage means that requests an address not owned by the data input/output means, extended address data is sent from the port at a specific address of the data input/output means, and then By providing an input/output port expansion means that allows data to be exchanged with an external data storage means via the same boat, the input/output port can be used only when necessary, without the need for a dedicated expansion terminal group. It is possible to obtain a microprocessor that can be expanded, resulting in great effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a microprocessor with an expansion board according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram of the main part of FIG. 941, FIG. 3 is a memory map, and FIG. 4 is a diagram of the invention. FIG. 5 is a block diagram of a microprocessor with an expansion board in another embodiment, and its memory map is shown in FIG. 1...1i'12 order ROM, 10...
Data bus, 13...General-purpose parallel input/output boat, 14...Expansion input/output boat, 18...
...Name of ALU0 agent Patent attorney Toshio Nakao and one other person WC2 Figure Nishiki Figure 3

Claims (1)

[Claims] a program storage means for storing a program consisting of a group of instructions to be executed sequentially; a data input/output means having a plurality of addresses, the address being specified by an instruction stored in the program storage means; and the program storage means. a calculation means for executing data calculations based on instructions sent from the computer; a data bus connecting the data input/output means and the calculation means; and a data bus that connects the program storage means to the data input/output means. When an instruction requesting an address that does not exist is sent, extended address data is sent from a port of a specific address of the data input/output means, and then data is exchanged with an external data storage means through the same port. A microprocessor having an expansion port, comprising input port expansion means for causing the input port to expand.