JPS5960791A - Bank switching system of bubble memory - Google Patents

Abstract

PURPOSE:To operate plural sheets of common bubble memory printed board units with just a single processor by comparing the designated contents of a hard bank with the designated contents of a soft bank which is designated during use, generating a bank signal only when the coincidence is obtained with above-mentioned comparison and using the bank signal as an I/O selection signal for bubble memory control. CONSTITUTION:The bank number set at a bank number setting circuit 11 is fed to a coincidence circuit 15, and this circuit 15 checks whether this input information is coincident with the bank designation done by the software. If the input information is coincident with the bank designation, a bank signal is delivered to a bank signal line 12. The contents of a latch 13 of bank signal latch number is common to bubble memory printed board units 2A and 2B, and the bank numbers set at the circuit 11 are different from each other. Therefore the bank signal is delivered only to bubble memory control circuits 3A and 3B of one bubble memory printed board unit. Thus the unit 2A or 2B can be freely used with switching in accordance with the bank number designated by an access requester.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention enables bank switching for each bubble memory printed board unit in a bubble memory bank switch system, particularly a bubble memory access control system.
The present invention relates to a bank switch system for bank memories that allows bank memories to be easily expanded without changing address assignment.

(2) Prior Art and Problems Magnetic bubble memories have recently come into widespread use because they can provide relatively high speed and large capacity.

FIG. 1 shows an example of a conventional bubble memory printed board unit. In the figure, l is the I10 bus, 2 is the bubble memory printed board unit, 3 is the bubble memory Φ control circuit, 4 is the bubble memory, 5 is the I10 select signal line, 6
7 represents a read/write signal line, and 7 represents a data bus.

The bubble memory printed board unit 2 includes a bubble memory control circuit 3, a bubble memory drive circuit,
A bubble memory 4 consisting of a bubble memory chip etc. is installed, and the memory capacity ranges from 256 Kbit to IMb, for example.
There are various types including those of IT. The bubble memory/printed board unit 2 can be viewed as one input/output device, and access to it is achieved by turning on the I10 select signal on the I10 select signal line 5 assigned to each bubble memory. This is done so that the bubble memory/printed board unit 2 is selected. This I
The 10 select signal may be considered to be a signal tone decoded on an address bus (not shown). Therefore, when using several puzzle memory/printed board units 2 in one processing device, conventionally it is necessary to allocate a different I10 send signal to each bubble memory/printed board unit 2. There was a problem that the printed board unit 2 was not common.

Therefore, it has not been possible to easily increase the memory capacity N in units of bubble memory printed board units.

(3) Object and Structure of the Invention The present invention aims to solve the above-mentioned problems, and the I10 select signal ff: can be used to process a plurality of common bubble memories and printed board units using one processing device, without changing the I10 select signal ff for each bubble memory printed board unit. The overall purpose is to make the printed board unit operational and to facilitate expansion of memory capacity. Therefore,
The present invention completely compares the contents set in hardware on the bubble memory printed board unit with the contents specified by the software bank specified by the software during use, and when they match. In this case, a bank signal is generated only for the bubble memory control, and this is used as the I10 select signal of the conventional bubble memory control. In other words, the bubble memory bank switch method of the present invention, in the baffle memory access control method, allows multiple bubble memory printed board units equipped with all bubble memory control circuits and bubble memory chips to be connected under a common interface. In addition to connecting to the bus, the bubble memory/printed board unit is connected to a bank number determination circuit in which a bank number assigned to each printed board unit is set, and a bank number specified by the access request source and the above-mentioned bank number. The bank number set in the bank number setting circuit is compared with the bank number set in the bank number setting circuit, and if they match, the corresponding bubble memory printed board unit (1) is selected. It is characterized by the ability to switch banks. Embodiments will be described below with reference to the drawings.

(4) Embodiment of the Invention FIG. 2 shows the configuration of an embodiment of the invention, and FIG. 3 is a circuit diagram of the bank select circuit shown in FIG. 2.

In the figure, numerals 1; t to 7 correspond to those in Fig. 1, ■0 is a bank select circuit, II is a bank number setting circuit, 12 is a bank signal line, 13 is a bank number latch, 14 is a decoder, and 15 is a match The circuit 16 represents an AND circuit.

Baffle memory printed board unit 2 people and 2B are
The following describes the case where there are two common bubble memory printed board units, but the same applies to the case where there are three baffle memory printed board units. =shi knit 2A
, 2B are bubble memory control times M3A, 3B
In addition to Bubble Memo'j 4 A, 41),
Bubble select circuit 10, A, 10 J3 and bank previous setting circuit 11 A, 1133 are all included (pull memory control circuit 3A, 31Lb)
- and bubble memo IJ4A, 4B are configured with 1 puncture number setting circuit 11 as in the conventional case.
A and IIB are configured such that the previous bank number assigned to the bubble memory printed board units 2A and 2B, respectively, can be set by hardware using a setting bin, for example. Identify only the two bubble memory printed board units) 2A and 2I3. In case, the bank number can be 1 bit, '0' for one and l' for the other.
+1# is assigned. In order to support three or more common bubble memory/printed board units, a bank number of 2 bits or more is provided so that it can be set. The information set in the bank number setting circuits 11A and IIB is always input to the bubble select circuit 10A and IOB. Check whether 2A4 or 2B is selected at the time of access,
This circuit outputs all bank signals to bank signal #J12A or 12B. For example, it is configured as shown in FIG.

The access requester sets the bank number latch 1 before accessing.
3, and set the bank number of the bubble memory/printed board unit to be selected at the time of access. In other words, the I10 select signal line 5 shown in FIG. Upper i107 rect signal and read/write signal line 6
The address of the bank number latch 13 to which all puncture numbers on the data bus 7 are written is
Since it is common to both the bank memory/printed board units 2A and 2B shown in FIG. 2, the same contents are taken in at the same time. The contents of the bank number latch 13 are decoded by the decoder 14 and sent to the matching circuit 1.
5 is input. This input means all bank specifications made by software.

On the other hand, the bank number set in the bank number setting circuit 11 is input to the matching circuit 15, and the matching circuit 15 checks whether this input information and the bank designation by the software match.

If they match, a full puncture signal is output to the bank signal line 12. The contents of the bank number latch I3 are common to each bubble memory/printed board unit 2A, 2B, but since the bank numbers set in the bank number setting circuit 11 are different, the bubble of one bubble memory/printed board unit Bank signals are output only to memory control circuits 3A and 3B. This bank signal may be considered to correspond to the I10 select signal input to the conventional bubble memory control circuit 3 described in FIG. Therefore, in the case shown in FIG. 2, ``Bubble memory/printed board unit) 2A or 2B'fr: can be freely switched and used depending on the bank number specified by the access request source.

Note that the bubble memory printed circuit board unit has many interface control registers, such as control registers, status registers, data registers, and address counters, although they are well known and are not shown in the figure, including the address bus. , byte counter, etc., making it possible to transfer multiple pages of data using DMA transfer, for example, using 64 bytes as one page.10 Conventionally, a system was equipped with multiple bubble memory printed board units. When installing, the addresses of the control registers, etc. had to be different for each address, but in the present invention, they can all be the same, making expansion easy.

(5) As described in detail, according to the present invention, the same bubble memory
By using all the printed board units, it becomes possible to easily expand the entire memory. Therefore, dynamic switching between bubble memory and printed board units can be easily performed.

[Brief explanation of the drawing]

Fig. 1 shows a conventional bubble memory/printed board UNISO; Fig. 2 shows an embodiment of the present invention, and Fig. 3 shows a second
A circuit diagram of the illustrated bank select circuit is shown. In the figure, 2 is a bubble memory printed board unit, 3 is a bubble memory control circuit, 4 is a bubble memory, 1
0 represents a bubble select circuit, ]1 represents a bank number setting circuit. Patent applicant Hiroshi Mori, agent patent attorney of Fujitsu Ltd.

Claims (1)

[Claims] In the bubble memory access control method, a common interface for a plurality of bubble memory printed board units equipped with a bubble memory e-control circuit and a bubble memory chip is also connected to a bus, and the bubble memory printed board units are When the bank number setting circuit in which the bank number assigned to each printed board unit is set is compared with the bank number specified by the access request source and the bank number set in the bank number setting circuit, and they match. The bubble memory ψ printed board unit is fully equipped with a bank selection circuit and a
A bubble memory bank switch method is characterized in that banks of the bubble memory can be switched according to a bank number specified by an access request source.