KR930004901B1 - Memory control unit of computer system by using dynamic ram - Google Patents

Abstract

The system for using a page mode DRAM controller to reduce an access time comprises a processor (10) having signals for dividing the memory area into program, data and stack areas, an area decoding unit (21) for decoding the memory area dividing signal from the processor, an address decoding unit (22) for applying an enable signal (50) to the unit (21), a first page mode DRAM controller (31) for controlling a first DRAM (41) for program area, a second page mode DRAM controller (32) for controlling a second DRAM (42) for data area, and a third page mode DRAM controller (33) for controlling a third DRAM (43) for stack area.

Description

Memory control device of computer system using DRAM

1 is a block diagram of an embodiment of the present invention.

2 is a block diagram of another embodiment of the present invention.

3 is a block diagram of another embodiment of the present invention.

4 is a diagram illustrating DRAM address allocation in FIG.

5 is a configuration diagram of a page mode DRAM controller used in the present invention.

* Explanation of symbols for main parts of the drawings

10: processor unit 20: decoder unit

21: area decoder 22: address decoder

30: memory control unit 40: memory unit

31,32,33: page mode DRAM controller 41,42,43: DRAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control apparatus of a computer system using a DRAM as a memory, and more particularly, to a memory control apparatus that reduces access time by using a page mode DRAM controller.

In general, an area accessed by a processor may be divided into a program area, a data area, and a stack area. The program area is the area where the instructions stored by the processor are stored. Most of these instructions are accessed sequentially, so it is very likely that two consecutive accesses are the same page within the program area.

The data area is an area where data manipulated by commands in the program area is designated. If the data is highly related, two consecutive accesses are likely to be the same page. In general, data manipulated in a short time is highly related to data, so even in a data area, there is a high probability that two consecutive accesses are the same page.

The stack area is the area accessed by the address specified by the stack pointer. In general, each access to this area increases or decreases the value of the stack pointer by one, so that two consecutive accesses in the area are mostly contiguous areas and are the same page. The probability is very high. In addition, the page mode DRAM controller used to effectively control the DRAM reduces the access time to about one third of the standard when the access area of the DRAM is the same page (same column address) as the previously accessed area. If the page is not accessed, the access time is increased. Therefore, the average DRAM access time is determined by the probability that the area accessed by the process is the same page as the previously accessed area.

Since the actual processor operation reads a program and manipulates data as the program instructs, the three regions are randomly accessed. The size of one page of DRAM is relatively small: 4096 bytes for one megabit DRAM and 8192 bytes for four megabit DRAM in a 32-bit wide processor, so these three areas are mostly on different pages.

Therefore, when one page mode DRAM controller is used, a different page from the previous access is accessed every time the access area is changed, and thus the performance improvement effect of the page mode DRAM controller cannot be expected.

The present invention has been made to solve the above problems, by assigning a program area, a data area, and a stack area to each of the different DRAM, and by configuring a page mode DRAM controller dedicated to only the corresponding area to each of the DRAM, The purpose of the present invention is to provide a memory controller of a computer system using a DRAM that reduces access time by minimizing the possibility of page change between two consecutive accesses even if the processor accesses a different area.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1, 2 and 3 are block diagrams showing a schematic configuration of a DRAM control apparatus implemented by the present invention, in which 10 is a processor, 21 is an area decoder, 22 is an address decoder, 31, 32, 33 denotes a page mode DRAM controller, and 41, 42, and 43 denote DRAMs, respectively.

Many recent processors have a signal for distinguishing a program area, a data area, a stack area, or a program area and a data area for each access. In the present invention, separate DRAMs 41, 42, and 43 are provided in each area as shown in FIG. And page mode DRAM controllers 31, 32, and 33 are allocated, and the region decoder 21 of the processor is decoded by the region decoder 21 to operate the corresponding DRAM controller.

That is, in FIG. 1, when the address to be accessed by the processor 10 is a DRAM area, the DRAM enable signal SO is generated through the address decoder 22 to be input to the area decoder 21, and the area decoder 21 is input to the area decoder 21. When receiving the DRAM enable signal SO, the area classification signal is decoded and the DRAM controller operation signals S1, S2, and S3 are output. If the area to be accessed is a program area, the program DRAM control signal S1 is output to operate the DRAM controller 1 31 to access the DRAM 1 41. If the data area is a data area, the DRAM control signal S2 is output. Then, the DRAM controller 2 (32) is operated to access the DRAM 2 (42). If the stack region is output, the DRAM control signal S3 for stack is output to operate the DRAM controller 3 (33) to access the DRAM 3 (43). In this configuration, each controller operates only in the program, data, and stack areas, and maximizes the probability of the same page between two consecutive accesses in each area, thereby increasing the ratio of page mode accesses and reducing the average DRAM access time. .

If there are only two area classification signals of the processor, a program area and a data area, two page mode DRAM controllers 31 and 32 may be configured as shown in FIG. In this case, since the stack area is included in the data area, the probability that two consecutive accesses in the data area are the same page may be slightly reduced.

FIG. 3 shows three page mode DRAM controllers 31, 32, and 33 which connect respective DRAMs as an example of another method, and each of the DRAMs 41, 42, and 43 has a different address area. Therefore, one of the three DRAM controllers operates according to the address area that the processor 10 wants to access and accesses the corresponding DRAM. The program is stored in the address area of DRAM 1 and the data is stored in the address area of DRAM 2. If it is allocated to the address area of DRAM 3, the same effect as in Fig. 1 can be achieved without the area decoder. That is, as shown in FIG. 4, the address area 1 is allocated to the DRAM 1, the address area 2 to the DRAM 2, and the address area 3 to the DRAM 3, and the program stores the data in the address area 1 and the stack in the address area 3. Then, if the processor wants to access the program area, it generates an operation signal e1 of the DRAM controller 31 through the address decoder to operate the DRAM controller 1 to access the DRAM 1 41, and to access the data area, the DRAM controller When the operation signal e2 of 2 32 is generated to access the DRAM 2 42 and the stack area is to be accessed, the operation signal 3 of the DRAM controller 3 33 is generated to access the DRAM 3 43. . The DRAM 1, DRAM 2, and DRAM 3 can be allocated to the program area, data area, and stack area by software, so that the area can be changed as necessary.

The same effects as in FIGS. 1 and 2 can be achieved without using the region separation signal, so that the processor can be used in a processor without the region separation signal. Each address area does not necessarily need to be a contiguous area, and the size can be adjusted as required by the capacity and number of DRAMs.

As shown in FIG. 5, the page mode DRAM controller used in the present invention inputs a DRAM access signal RAMSEL, a read and write signal R / W, and a reference clock CLK to receive an address divider control signal. A controller generating COLAD), DRAM control signals RAS and DAS, and an access completion signal TERM, and an address applied to the address line of the DRAM by inputting a row address and a column address according to the control signal COLAD of the controller. And a divider, a latch for storing a row address under control of the controller (RAS), and a comparator for comparing the old column address and the new column address stored in the latch to the controller.

As described above, the present invention minimizes the probability of page change by using a plurality of page mode DRAM controllers according to the type of access area, thereby increasing the page mode access ratio, thereby reducing the average access time during DRAM access.

Claims (9)

And a processor 10 having area discrimination signals (program, data, stack area), wherein the first, second and third DRAMs 41, 42, 43 are separately provided in the program area, data area and stack area. A memory control apparatus of a computer system which is used as a memory, comprising: area decoding means (21) for decoding a memory area division signal from the processor (10); Address decoding means (22) connected to said processor (10) via an address bus and for applying an enable signal (SO) to said area decoding means (21); First page mode DRAM control means (31) connected to said area decoding means (21) and an address bus and for controlling a first DRAM (41) assigned to an area in said program; Third page mode DRAM control means (32), connected to said area decoding means (21) and an address bus, for controlling a second DRAM (42) assigned to said data area; And third page mode DRAM control means (33), connected to the area decoding means (21) and the address bus, for controlling a third DRAM (43) allocated to the stack area. Memory control device comprising a. 2. The apparatus of claim 1, wherein the first to third page mode DRAM control means (31, 32, 33) comprises: address distribution means for inputting a row address and a column address to the address line of the DRAM, respectively; Control means for controlling the address distribution means and DRAM under the control of the processor 10; Latch means for temporarily storing a row address under control of the control means; And comparing means for comparing the old column address and the new column address resisted by the latch means to output to the control means. Memory control device, characterized in that configured to include. The method of claim 2, wherein the area decoding means 21 receives a DRAM enable signal SO from the address decoding means 22, decodes an area classification signal from the processor 10, and decodes a head DRAM control signal. And a memory controller configured to generate S1, S2, S3). A processor 10 having a signal for distinguishing areas of a program area and a data area is provided, the first DRAM 41 is allocated to the program area, and the second DRAM 42 is allocated to the data and stack areas, and used as a memory. A memory controller of a computer system, comprising: area decoding means (21) for decoding a memory area classification signal from said processor (10); Address decoding means (22) connected to said processor (10) via an address bus and for applying an enable signal (SO) to said area decoding means (21); First page mode DRAM control means (31), connected to the area decoding means (21) and the address bus, for controlling a first DRAM (41) assigned to the program area; And second page mode DRAM control means (32) connected to said area decoding means (21) and an address bus for controlling a second DRAM (42) allocated to said data and stack areas. Memory control device comprising a. 5. The apparatus of claim 4, wherein the first and second DRAM control stages (31, 32) comprise: main distribution means for inputting a row address and a column address to the address line of the DRAM, respectively; Control means for controlling the address distribution means and DRAM under the control of the processor 10; Latch means for temporarily storing a row address under control of the control means; And comparing means for comparing the old column address stored in the latch means with the new column address and outputting them to the control means. Memory control device, characterized in that configured to include. The method of claim 5, wherein the area decoding means 21 receives the DRAM enable signal SO from the address decoding means 22, decodes the area classification signal from the processor 10, and decodes the corresponding DRAM control signal. And S1, S2). A memory control apparatus of a computer system having a processor 10 having no area discriminating signal and first, second, and third DRAMs 41, 42, and 43 having different address areas, the address bus being provided via an address bus. Address decoding means (20) coupled to the processor (10); First page mode DRAM control means (31) connected to the address decoding means (20) and the address bus and controlling the first DRAM (41); Second page mode DRAM control means (32), connected to the address decoding means (20) and the address bus, for controlling the second DRAM (42); And third page mode DRAM control means (33) connected to the address decoding means (20) and the address bus, for controlling the third DRAM (43). Memory device comprising a. 8. The method of claim 7, wherein the first to third page mode DRAM control means (31, 32, 33) comprises: main distribution means for inputting a row address and a column address to the address line of the DRAM, respectively; Control means for controlling the address distribution means and the DRAM under the control of the processor (10); Latch means for temporarily storing a row address under control of the control means; And comparing means for comparing the old column address stored in the latch means with the new column address and outputting them to the control means. Memory control device, characterized in that configured to include. 9. The memory control apparatus according to claim 8, wherein each page mode DRAM control means (31, 32, 33) is configured to operate by receiving an enable signal from said address decoding means (20).