JPS60129854A - Address bus controller - Google Patents

Abstract

PURPOSE:To make it possible that a CPU which controls an address bus of x- number of bits accesses an address space of m-number of bits (m>x), by providing address banks having extended addresses and an address bank selecting decoder. CONSTITUTION:A CPU10 can access directly address information consisting of x- number of bits and is connected to address banks 14-1-14-n' through an address bank selecting decoder 15. Banks 14-1-14-n' have extended addresses y1-yn' including upper n-number of bits of address information, and the decoder 15 outputs selecting signals a-1-a-n'. That is, the decoder 15 assignes upper n-number of bits of the CPU10 to address bank selecting bits and decodes upper n-number of bits on an address bus 12 and selects address banks and outputs their contents. Thus, the extended address of y-number of bits including upper n-number of bits is set to each address bank, and the CPU10 which controls the address bus of x-number of bits can access the address space of m-number of bits (m> x).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address bus control device that accesses an address space wider than that accessible by a CPU (Central Processing Unit).

Conventional configurations and their problems In recent years, the field of information processing using microcomputers has
It has developed at a remarkable pace, as exemplified by personal computers. As semiconductor technology advances, the amount of information handled by microcomputers is becoming more diverse and huge, including databases and image processing.

The conventional address bus control system will be explained below.

FIG. 1 shows a configuration diagram of a conventional address bus control device. 1 is the directly accessible real address information x
A CPU with bits can access 2x address space. 2 is a main storage section (hereinafter abbreviated as memory) in which data, programs, etc. are stored. 3 is the Ilo region.

4 is an address bus composed of xbits.

The operation of the conventional address bus control device configured as described above will be explained below.

The following description assumes that the address information x held by CPU 1 is 18 bits. Address bus 4 is 2 = 256KWord (
or Byte), with an address space of cpul
The address information outputted from the CPU 1 was directly reflected on the address bus 4, accessed the memory 2 or the 1/6 area 3, and the CPU 1 executed the program and processed the data.

However, in the above configuration, the address information output by cpu 1 becomes the access space, and cpu 1
ul can only access 2X address space. c.
Nowadays, as the amount of information handled by PUs becomes more diverse and enormous, even APUs with excellent functions may have to be abandoned due to the narrow address space.

As a solution to this problem, I was wondering if it would be possible to increase the amount of address information output by the CPU, but this is not an easy task.

Purpose of the Invention The present invention solves the above-mentioned conventional problems, and
The apu that controls the address bus is mbit (m>X
) The object of the present invention is to provide an address bus control device that makes it possible to access the address space of .

Structure of the Invention An object of the present invention is to provide an address bank for holding extended addresses, an upper nb of a CPU having an address bus
This is an address bus control device equipped with an address bank selection decoder that assigns it to the address bank selection bit, decodes the upper n bits of the address bus, selects the address bank, and outputs the contents to the address bus. An extended address y bit containing n bits is set, and the CPU accesses an address space of 2n, but in reality it can access an address space of 2m.

DESCRIPTION OF EMBODIMENTS FIG. 2 is a block diagram of an address bus control device according to a first embodiment of the present invention. In Figure 2, IQ is a CPU with xbits of address information that can be directly accessed,
Reference numeral 11 denotes a main storage section (hereinafter abbreviated as memory) in which data, programs, etc. are stored.

12 is a CPU address bus output by CPU 1;
13 is a system address bus to which the memory 11 etc. are actually connected, and the address information is m bit (m) x
). An address bank selection decoder 15 decodes the upper n bits of the CPU address bus 12, and outputs selection signals a-1 to a-n'(n'-2n). 14-1 to 14-n' are a plurality of address banks 1 to n' that hold extended addresses y1 to y including the second Hbit, and select signals a-1 to a-n' [Yo extended address Output y1-3'nt. Each address bank is assigned to I10 addresses. 16 is a system data bus, 17 is an /δ decoder connected to the system address bus, and a latch signal b-1 for determining the contents of each address bank 1 to n'.
~l, , / is output. Address bank 14-1~1
4-n' holds the contents of the system data bus by these latch signals b-1 to b-n'.

Regarding the address bus control device of this embodiment configured as described above, x=18, n=2, n'=2n=2
2=4. m=24 (16M address space) y=m
-(x-n) = 8 (y is called extended address) I/δ address of each address bank 14-1 to 14n' is A
DI to ADn' will be explained as an example.

First, address banks 14-1 to 14n' are set.

Address bank 14-1 has 000○0○00=x'o
o', 7 dos vs bank 14-2 is ○○000101
=x'05', ○11 in address bank 14-3
10○01 =X'51', address bank 14-
Suppose that we want to set 10101100=x'AC' for n'. Each address bank 14-1 to 14n' is
Assigned to address (AD 1 to AD n');], x '00 is assigned to address AD1
', the I15 decoder 17 outputs the latch signal b
-1 is output. The latch signal b-1 causes the address bank 14-1 to read the contents xl on the system data bus 16.
○Keep 01. I/δ address AD2 x1○5
' When Ilo decoder 17 writes decode signal b
-2 is output. The address bank 14-2 holds the contents x'05' on the system data bus 16 by the latch signal b-2. Similarly, address bank 14-2,
14n' can also be set.

FIG. 3 shows a map diagram of address control according to an embodiment of the present invention. CPU connected to system address bus 13
Address bus 12 is x-n (18-2=16) bits
It is. Therefore, the address space at 2:64 is cpu
1○ can be used without any awareness.

These 64 units are called segments. The CPU address space that can be accessed by CPU 11 is x'o'
~x'5FFFF' are used as segments 0 to 3, respectively (FIG. 3, CPU address space).

FIG. 4 shows an output table of the address bank selection decoder 15. When n=OO(x'O'), the selection signal a-1 is output, and when n=11 (x'3'), the selection signal an' is output.

When CPU 1○ accesses segment 0, address bank selection decoder 15 outputs selection signal a-1 because it is n-○○. The selection signal a-1 causes the address bank 14-1 to transfer its contents x'oo' to the extended address y.
, output to the system at V snow (S13. cp
When u 11 accesses segment ○, it accesses system address space x101 to x'FFFF' (FIG. 30).

When cpull accesses segment 1 space,
Since n=01, the address bank selection decoder 15 outputs the selection signal a-2. Address bank 14-2 receives extended address y 2 (x'
O51) Output on the entire system address bus 13. cpull is the system address space X'05000
0'-x'05FFFF' will be accessed (
Figure 3 1).

Similarly, when cpull accesses segment 2, the system address space x '710000' to x'71F
When FFF' is segment 3, the system address space xIAC0000' to X'ACFFFF' is accessed. FIG. 5 shows an address correspondence diagram.

As described above, according to this embodiment, the address bank holding extended addresses and the upper n bits of the address bus xbit are allocated for selecting the address bank, the upper n bits are decoded, and an address bank selection signal is output. By providing an address bank selection decoder,
By expanding the CPU's address space, infinite space can be arbitrarily accessed to change the contents of the address bank.

An address bank according to a second embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 shows a configuration diagram of an address bank of an address bus control device showing a second embodiment of the present invention.

In the figure, a bank register 21 holds the CPU address bus 12 and a deviation value as an extended address, holds the contents of the system data bus 16 in response to a launch signal b', and outputs an extended address y'.

22 is an adder that adds the CPU address bus 12 and the extended address y', and outputs the content to the system address bus 13 in response to the selection signal a'.

Figure 7 shows the extended address y' and the CPU address bus 12.
A corresponding diagram is shown. x=18, y'=8, m=2
3.

Addition corresponding bits to CPU Upper 4 bits of address 12
.

The lower abit of extended address y' will be explained as an example. The selection signal a/ and latch signal b' are the same as in the first embodiment.

The launch signal b' causes the contents of the system data bus 16 to be held in the bank register 21.
outputs the extended address y'. The adder 22 is a CPU
Address bus 12 and extended address y' are added, and when selection signal a' is input, added address m' is output to system address bus 13.

For example, if the content X of the CPU address bus 12 is x'29
? ? ? Extended address y with I (?:Don'tcare)
' is X'9C', addition address m' is x'299
? ? ? ' becomes.

As described above, according to this embodiment, the address bank is provided with a bank register that holds an extended address and an adder that adds the contents of the bank register and the contents of the CPU address bus, thereby making the contents of the bank register deviate. address extension can be performed.

In both embodiments, the extended address y was set to 8 bits, but
Any number of bits is fine. By changing the bits that hold the extended address, an infinite address space can be easily accessed.

Also, n = 2 bits and the number of address banks is 4, but the number of address banks may be 1, and n = 3.4.
...There is no problem even if the number of binding addresses is increased.

Effects of the Invention The address bus control device of the present invention has an address bank holding extended addresses and a c
The upper n bits of pu are allocated for address bank selection, and the upper n bits of the address bus? (By providing an address bank selection decoder that decodes and selects the address bank, the CPU can access any address space expanded from the 2n address space that can be directly accessed, and even a CPU with a narrow address space can handle a large amount of information.) can be handled, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a conventional address bus control device, FIG. 2 is a block configuration diagram of an address bus control device in the first embodiment of the present invention, FIG. 3 is a map diagram of address control, and FIG. 4 5 is a correspondence diagram of the output of the address bank selection decoder, FIG. 5 is a correspondence diagram of bH between the CPU address bus and extended addresses, and FIG. 6 is a block configuration diagram of the address bank of the address bus control device in the second embodiment of the present invention. , Figure 7 shows the relationship between the CPU address bus and the extended address.
It is an IT correspondence diagram. 14-1・14-2...+4-n'・14'...
. . . Address bank, 15 . . . Address bank selection decoder, 17 . . . I 10 decoder. Name of agent: Patent attorney Toshio Nakao and one other IR
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] The address bank that holds the extended address retains the x bits of the address bus and allocates the upper n bits of the CPU to the address bank selection bits, and
t, selects the address bank, and outputs its contents to an expanded address bus; and an input/output decoder that outputs a latch signal that sets the contents of the address bank. address bus controller.