JP3205564B2 - Memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU for converting a program created by a user into a machine language by using the CPU and executing the program.
The present invention relates to a memory circuit used in a system.

[0002]

2. Description of the Related Art Conventionally, in a CPU, a memory space (number of addresses) has been expanded in order to process a large amount of data. FIG. 9 shows a conventional example. In this conventional example, three registers of an area register 1, a common register 2, and a bank register 3 are used, and 64 registers of an 8-bit CPU are used.
K-byte memory space (logical address) LA is divided into three areas, which are divided into 1-Mbyte memory space (physical space)
Projected to PA.

[0003]

According to this method, the bank area and the common area have a physical space PA of 1 Mbyte.
However, since the area register 1 divides the area using the 12th to 15th bits of the logical address LA, the area can be divided only in units of 4 Kbytes. When divided, a large number of area registers 1, bank base registers 2, and switching circuits for the comparator 4 and the adder 5 are required, and the circuit becomes complicated and large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to project a large number of areas allocated to logical addresses with a sufficient configuration to a real memory of physical addresses with a minimum configuration. It is to provide a memory circuit that can be used.

[0005]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention provides a memory circuit which reads and writes data from a CPU using a plurality of memories and decodes a CPU address to detect a specific area. And an address decoding circuit for converting an address output from the CPU into an actual memory address based on an area signal of the address decoding circuit output when a specific area is detected and a control signal for controlling allocation in the memory. An offset circuit for generating an offset value, an addition circuit for adding an output from the offset circuit and an address from the CPU to output a memory address, and a select signal for selecting an actual memory from the area signal and the control signal And a memory select circuit that outputs
A first control signal for allocating different processes of different memories to the same area of the address space of the CPU, and a second control signal for exchanging different processing areas of the memory corresponding to the two function areas of the address space of the CPU. Using, C
The address from the PU is converted and assigned to an arbitrary address in an arbitrary memory.

[0006]

According to the present invention, an address decode circuit, an offset circuit, a memory select circuit, and an adder circuit are provided for receiving an address from a CPU, and different processes of different memories are allocated to the same area of the CPU address space as a control signal. Using the first control signal and the second control signal for exchanging two processing areas of the memory corresponding to the two function areas of the address space of the CPU, it is possible to allocate to an arbitrary address of an arbitrary memory. Therefore, a system having a plurality of memory maps can be handled by the CPU with the same memory map.

[0007]

The present invention will be described below with reference to examples. Figure 1
4 shows a circuit block of the embodiment, and shows an address of a CPU.
A_Ten~ A₁₇Decodes a specific area to detect
Decode circuit 10 for outputting a signal and the area signal
And the control signal for controlling the allocation in the memory, the CP
Address A output from U_Ten~ A₁₇The actual memory
Generate offset value to convert to address off
Set circuit 20 and output from offset circuit 20
OF₁₄~ OF₁₁And address A from CPU_Ten~ A₁₇Add
Address of memory A ₁₁~ A₁₄Times to output
The path 30, the actual memo from the area signal and the control signal
Memory select that outputs a select signal to select memory
Circuit 40.

The control signal includes a type 50K / 25K signal (TYPE signal), which is a first signal for switching the actual memory arrangement, and a specific area of the memory arrangement of the CPU which is switched between two areas of the actual memory. Compile / SYS signal (CS signal) as a second signal for use
And a work B as a third signal for exchanging and using two areas of the actual memory with two specific areas of the CPU.
/ A signal (BA signal), and the first and second signals
However, different notes are stored in the same area of the CPU address space.
Corresponding to a first control signal for allocating different processes,
The third signal is an area for two functions in the CPU address space.
Swap different processing areas of memory corresponding to the
This corresponds to a second control signal.

The select signals are CCSY and CSM.
0, CSM1, and CSM2. FIG.
3 and 4 show different memory maps of the memories handled by the memory circuit of the present invention. The difference between the memory map shown in FIG. 2 and the memory map shown in FIG. In FIG. 3, the area of the system has been increased to 62 Kbytes. And the memory map of FIG. 3, FIG. 4 is a memory map of FIG. 4
It is more one is SRAM, compilation area is 32K
The bytes and work area have increased to 8K bytes, and the user ROM area has increased to 16K.

Here, the area of the memory map corresponding to the above-mentioned specific area is from 08000 to 0F7F of the CPU.
3 and 4 according to the CS signal.
Area is allocated to the system allocated to ROM and SRAM
Switch to the assigned compilation. The workpiece W ₁ and two specific regions of the above, indicates a region of the workpiece W _2, it can be handled by interchanging the area of the work WA and workpiece WB in the SRAM by the BA signal.

In these maps, the CPU area is larger than the memory area. However, in the memory area, the memory select signal continues to be output, and the memory address returns to 0 when the address exceeds the maximum address. For example, if access is made from address 38000 of the CPU in the memory map shown in FIG. 2, the compile area of the SRAM, the user RAM, the works WA and WB, and the stack are seen in this order.

Table 1 shows a control signal in the memory select circuit 40 and a table of a memory select signal for the CPU address. Table 2 shows a control signal in the offset circuit and an offset value for the CPU address. In Table 2, the offset value is represented by 16 bits.
A total of 4 bits are used.

[0013]

[Table 1] Table 1 shows that the memory select circuit of FIG.
A signal CS for selecting an actual memory in response to the signal S
How SY, CSM0, CSM1, CSM2 output
It is a table showing whether or not it is performed. The CSSY of FIGS. 2 to 4
Select an SRAM to which only compilation is assigned
Signal, CSM1 is assigned only to the compilation of Fig. 4.
To select the selected SRAM, CSM2 is EPRO
This signal selects M. Fig. 3 when TYPE is 0
08000 to 0F7FF depending on the CS signal
Area is ROM (CSSY) and SRAM (CSMO)
Can be switched to Also, when TYPE is 0 corresponds to FIG.
The area from 08000 to 0F7FF depends on the CS signal.
A) ROM (CSSY) and compile-only SRAM
(CSM1). Figure 2 shows TYPE in Table 1.
Example of memory map when 0 and CS are fixed at 1
You.

[0014]

[Table 2] Table 2 shows that the offset circuit 20 uses TYPE, CS and BA
Supply to actual memory for CPU address by signal signal
Table 1 shows what happens to the addresses to be
In addition, each area of the CPU address space in FIGS. 2 to 4
Shows how it corresponds to the actual memory.
The shaded area in the table indicates that the address from the CPU is stored in memory as it is.
Indicates that it will be supplied. For example, if TYPE is 0, C
When S is 0 and BA is 0, the CPU address space in FIG.
0000-0F7FF is 000 of ROM (CSSY)
0F800 of CPU address space corresponding to 0 to F7FF
0F8FF is 3800-3B of SRAM (CSM0)
It corresponds to FF. BA is 0
When the work W ₁ of the CPU address space is SRAM (CS
Of CPU address space to work WA of M0) work W ₂
Corresponds to the work WB of the SRAM (CSM0)
However, if BA is set to 1, the work W _{1 in the} CPU address space
Is the CPU address to the work WB of the SRAM (CSM0)
Work WA work W ₂ is a SRAM (CSM0) of space
Can be replaced by BA signal.
You. Numeric values in parentheses in Table 2 are turned off to perform the above-mentioned actions.
An offset value that will be generated by the set circuit 20, hexadecimal
It is represented by four digits of 16 bits. This value is the number of times
Is added to the address of the CPU in the path 30 and supplied to the memory.
You. In the shaded portion in Table 2, the offset value is 0, and
The address is directly supplied to the memory. Offset of Table 2
Offset against the A ₁₀ from A ₀ As can be seen in Tsu bet value
In always 0, A ₁₅ is larger than the case 32K bytes of Example
ROM (system) is the only area that handles
When the CS signal is 0 and the system is selected,
Since it may be supplied less, from A ₁₁ A ₁₄ only
It is good to add the offset value.
The circuit shown in FIG. And the operation of each signal line is omitted
But using specific address and control signals
Are as shown in Tables 1 and 2 above.
You. The TYPE signal is physically at 1 or 0 level.
It is supplied fixedly and determined from the time the system is turned on.
CS and BA signals are output from CPU output port as needed
Output by software processing. The TYPE signal is off.
From the CPU by the offset circuit 20 and the addition circuit 30
Can handle systems with different memory capacities in the same way,
There is no need to develop multiple software for
By shortening the development period of affiliated products with different program capacities
When the software changes,
Maintainability such as fixing bugs can be greatly improved
You. CS signal is only signal output and the same address of CPU is empty.
Different processing can be realized between
In case of U etc., switching of memory space is required at 64k bytes
Performs complicated circuits and complicated software processing as before
This causes a reduction in the original processing speed and causes malfunctions.
However, the processing speed and the reliability can be improved. BA
Signals are processed separately by the same function, for example, by two-channel communication.
This is effective when handling different communication protocols. For example
Communication area of the W ₁ of the CPU address space channel 1
A, W ₂ is the communication area of channel 2 or W of SRAM
A is the processing area of protocol A, WB is the processing area of protocol B
Used by assigning it to a processing area, etc.
Communication is clearly separated and instantly switched
Response (processing) speed is improved.

FIGS. 5, 6, 7 and 8 show address decoding.
Circuit 10, memory select circuit 40, offset circuit
20 and a specific circuit of the adder circuit 30, respectively.
The address decode circuit 10₁₇, A₁₆, A_Fifteen
And the COMP signal indicating the compilation area
Address A₁₇, A₁₆And address A_FifteenInversion of
No.NA_FifteenThe logical AND value of
And address A₁₇Inverted signal NA of₁₇And address
A₁₆, A_FifteenAND with the address A ₁₄, A₁₃
The logical sum of₁WRK indicating₁Signal
You. Address A₁₇Inverted signal NA of₁₇And address
A₁₆, A_FifteenAND with the address A ₁₃Inversion of
No.NA₁₃And address A₁₄The logical sum of_TwoTo
WRK shown_TwoSignal. Further, the inverted signal NA₁₇And a
Dress A₁₆Inverted signal NA of₁₆And address A_FifteenNegation logic
Product value and address A₁₄~ A₁₁Inverted signal of AND value with
And address A_TenS indicating the stack area by the logical sum of
Create a TCK signal. Further, the above inverted signal NA₁₇, N
A_Fifteen, Address A₁₆USER signal to identify user area by
Signal and inverted signal NA₁₇, NA₁₆And address A_FifteenNo
Constant AND value and the address A₁₄~ A₁₁With the logical product value of
The OR value is used to identify the compile area of the system.
P signal and inverted signal NA₁₇~ NA_FifteenNegation of
Then, a SYST signal indicating the system area is generated.

The offset circuit 20 has a SYCP signal indicating the five areas from the address decoder circuit 10,
TCK signal, WRK ₁ signal, constituting WRK ₂ signal, and the COMP signal, and TYPE signal of the control signal, and the CS signal, a logic circuit for generating an offset signal OF ₁₁ ~OF ₁₄ by using the BA signal. The memory select circuit uses the SY
CP signal, STCK signal, WRK ₁ signal, WRK ₂ signal,
Each inverted signal of the COMP signal NSYC signal, NSTC signal, NCOM signal, NWK ₁ signal, NWK ₂ signal, and T
YPE signal and its inverted signal NTYP, compile / S
The YS signal and its inverted signal NCS, and the inverted signals NUSE and SY of the USER signal from the address code circuit 10
CCSY, CSM using the inverted signal NSYS of the ST signal
0, CSM1, and CSM2 are generated.

The adder circuit 30 includes addresses A _{11 to} A ₁₄ ,
It is to obtain an address output A ₁₁ to A ₁₄ of the memory by using the offset signal OF ₁₁ ~OF _14. As shown in the specific circuit described above, in the embodiment, the entire circuit, particularly, the offset circuit 30 does not refer to the offset table but can be configured by a logical circuit of a logical product and a logical sum.

According to the present invention, in a memory circuit for reading and writing data from a CPU using a plurality of memories, an address decode circuit for decoding a CPU address and detecting a specific area, and outputting a signal when a specific area is detected. An offset circuit for generating an offset value for converting an address output from the CPU into an actual memory address based on a region signal of an address decode circuit to be executed and a control signal for controlling allocation in the memory; and an output from the offset circuit. And an adder circuit for adding an address from the CPU to output an address of the memory, and a memory select circuit for outputting a select signal for selecting an actual memory from the area signal and the control signal.
A first control signal to allocate the different processing of different memories in the same area CPU address space, and a second control signal to switch the area of the different processing of the memory corresponding to the area of the two functions of the CPU address space Is used to convert the address from the CPU and assign it to any address in any memory.Therefore, it is possible to project a large number of areas assigned to logical addresses with sufficient margin onto the real memory of physical addresses with the minimum configuration. For systems with multiple memory maps
The PU can handle the same memory map, and special handling can be performed for a specific area so that the system can be easily processed. This increases the efficiency of system software development and enhances the functions of the CPU. This has the effect of maximizing the draw-out, and also has the effect of reducing the cost of the system since the memory can be configured with a minimum capacity.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention.

FIG. 2 is a first correspondence between a memory map and a real memory according to the first embodiment;
FIG.

FIG. 3 is a second correspondence between the above memory map and the real memory.
FIG.

FIG. 4 is a third correspondence between the memory map and the real memory according to the first embodiment;
FIG.

FIG. 5 is a specific circuit diagram of the address decode circuit of FIG. 1;

FIG. 6 is a specific circuit diagram of the offset circuit of FIG. 1;

FIG. 7 is a specific circuit diagram of the memory select circuit of FIG. 1;

FIG. 8 is a specific circuit diagram of the addition circuit of FIG. 1;

FIG. 9 is a circuit block diagram of a conventional example.

[Explanation of symbols]

 Reference Signs List 10 address decode circuit 20 offset circuit 30 adder circuit 40 memory select circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/00-12/06 G06F 13/16-13/18

Claims (1)

(57) [Claims] 1. A memory circuit for reading and writing data from a CPU using a plurality of memories, an address decoding circuit for decoding a CPU address to detect a specific area, and an address output when a specific area is detected. An offset circuit for generating an offset value for converting an address output from the CPU into an actual memory address based on a region signal of the decode circuit and a control signal for controlling allocation in the memory; and an output from the offset circuit and the CPU. An adder circuit for adding an address from the memory and outputting a memory address; and a memory select circuit for outputting a select signal for selecting an actual memory based on the area signal and the control signal. The first to allocate different processes of different memories to the same area of space Using a control signal, a second control signal to switch the area of the different processing of the memory corresponding to the area of the two functions of the address space of the CPU, CPU
A memory circuit, which converts an address from a memory and assigns it to an arbitrary address of an arbitrary memory.