KR20010082982A - Interrupt Management System and Interrupt Management Method using Expanded Interrupt Vectors - Google Patents

Abstract

PURPOSE: A system and method for controlling an interrupt using an expanded interrupt vector is provided to process interrupts being generated from more interrupt sources than interrupt sources responding to an interrupt vector area provided from a micro processor. CONSTITUTION: An expansion interrupt vector recording unit(19) records address information of a plurality of interrupt processing routines and comprises a plurality of vectors storing address information of each interrupt processing routine. An interrupt polling unit(18) selects one interrupt out of non-processed interrupts and extracts and outputs address information of an interrupt processing routine corresponded to the selected interrupt from the expansion interrupt vector recording unit(19). A shadow register(17) stores output information of the interrupt polling unit(18). An address remapping unit(13) receives address information of the original interrupt vector being generated from a micro processor(11) and generates address information of the shadow register(17) instead of the address information of the original interrupt vector.

Description

Interrupt Management System and Interrupt Management Method using Expanded Interrupt Vectors

The present invention relates to an interrupt control system, and more particularly, to an interrupt control system using an extended interrupt vector to handle a plurality of interrupts.

When the interrupt is controlled by the microprocessor, the interrupt vector region is generally set for rapid processing, and the interrupt processing routine is referred to by referring to the interrupt vector mapped according to the interrupt source when the interrupt occurs. Branch to. That is, address information indicating an interrupt processing routine is stored in advance in the interrupt vector. When an interrupt occurs, the microprocessor reads the contents stored in the interrupt vector to branch to the interrupt processing routine. However, the size of the interrupt vector area basically provided by the microprocessor is limited. Therefore, if a microprocessor needs to handle more interrupt sources than the interrupt vectors basically provided, an additional software or hardware solution is needed.

One software solution is to group multiple interrupt sources and map them to a single interrupt vector. When an interrupt occurs, one interrupt is determined by priority among unprocessed interrupts belonging to the group in the interrupt processing routine. The above decision method is a software polling method. If one interrupt is determined, branches back to the interrupt processing routine corresponding to the determined interrupt. Therefore, this software solution has no additional hardware burden, but it takes a long time to process the interrupt.

Even in the hardware solution, grouping multiple interrupt sources is the same as in the software solution. However, the method of determining the interrupt of one of the unprocessed interrupts belonging to one group is not a software poll but a hardware poll. However, even with hardware polling, branches at least twice to allocate an interrupt handling routine. As described above, a method of using an extended interrupt vector has been conventionally proposed to solve the problem of branching more than once. However, the conventional method of using the extended interrupt vector has a disadvantage in that the area on the memory where the extended interrupt vector can be located is limited and the processing speed is slow.

Therefore, when processing more interrupt sources than the interrupt sources corresponding to the interrupt vector area provided by the microprocessor, the conventional technology has a problem that the interrupt processing time is long or the location of the extended interrupt vector is limited.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an interrupt control system for rapidly processing interrupts generated from a greater number of interrupt sources than an interrupt source corresponding to an interrupt vector region provided by a microprocessor.

Another object of the present invention is to provide an interrupt control method for rapidly processing interrupts generated from a greater number of interrupt sources than an interrupt source corresponding to an interrupt vector region provided by a microprocessor.

1 is a diagram illustrating an interrupt control system according to an exemplary embodiment of the present invention.

2 is a flowchart illustrating an interrupt control method according to an exemplary embodiment of the present invention.

FIG. 3 is a diagram illustrating an interrupt process according to the interrupt control method of FIG. 2 and an interrupt process according to a conventional software polling method.

According to an aspect of the present invention, a microprocessor generates address information of a predetermined original interrupt vector when a predetermined interrupt processing request signal is generated, and among the plurality of interrupt processing routines, according to the information corresponding to the address information. An interrupt control system for assigning interrupt handling routines. An interrupt control system according to a preferred embodiment includes an extended interrupt vector recorder for recording address information of the plurality of interrupt processing routines, the extended interrupt vector recorder comprising a plurality of vectors storing address information of each interrupt processing routine; An interrupt polling unit for selecting any one of the unprocessed interrupts according to a predetermined rule and extracting and outputting address information of an interrupt processing routine corresponding to the selected interrupt from the extended interrupt vector; A shadow register for storing output information of the interrupt polling unit; And an address remapping unit configured to receive the address information of the original interrupt vector generated by the microprocessor and generate address information of the shadow register in place of the address information of the original interrupt vector.

The present invention for achieving the above another technical problem relates to a method for controlling an interrupt generated by using an extended interrupt vector. According to a preferred embodiment, an interrupt control method includes: A) storing address information of interrupt processing routines in the extended interrupt vector; B) generating address information of a predetermined original interrupt vector; C) the address remapping unit receives the address information of the original interrupt vector, and generates address information of a predetermined shadow register instead of the address information of the original interrupt vector; And D) assigning an interrupt processing routine indicated by address information input to the shadow register. And, before the step D), the shadow register is input with the address information of any one of address information of the interrupt processing routine stored in the extended interrupt vector according to an unprocessed interrupt.

By the interrupt control system of the present invention, interrupts generated from a plurality of interrupt sources can be processed quickly. And, the extended interrupt vector in the interrupt control system of the present invention can be freely located on the memory.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, for convenience of description, signals and components that perform the same roles throughout the drawings are denoted by the same reference numerals and reference numerals.

1 is a diagram illustrating an interrupt control system according to the present invention. Referring to this, the interrupt control system according to the preferred embodiment includes an address remapping unit 13, a shadow register 17, an interrupt polling unit 18, and an extended interrupt vector unit 19.

The interrupt control system of this embodiment relates to an interrupt control system in a system incorporating a microprocessor 11 that generates address information of the original interrupt vector 15 when an interrupt processing request signal INT_REQ is generated. The original interrupt vector 15 is an interrupt vector that the microprocessor 11 basically refers to when the interrupt processing request signal INT_REQ is generated. Therefore, in general, address information indicating an interrupt processing routine is stored in the original interrupt vector 15. The interrupt processing request signal INT_REQ is a signal for requesting the microprocessor 11 to process an interrupt. In general, an interrupt processing request signal INT_REQ is generated when there is an unprocessed interrupt among interrupts generated from an interrupt source.

The extended interrupt vector recording unit 19 is a memory area for storing address information of a plurality of interrupt processing routines, and is composed of a plurality of extended interrupt vectors. Each vector of the extended interrupt vector recording unit 19 stores address information of each interrupt processing routine. In this specification, the extended interrupt vector recording unit 19 is composed of the first to nth extended interrupt vectors.

The interrupt polling unit 18 selects one interrupt among unprocessed interrupts according to a predetermined rule. Preferably, the interrupt polling unit 18 selects one interrupt in hardware according to an interrupt priority among interrupts that are not masked among unprocessed interrupts. Masking is a decision on whether or not to handle an interrupt when an interrupt occurs. The interrupt polling unit 18 hardware-selects one extended interrupt vector storing the address information of the interrupt processing routine corresponding to the selected interrupt from the extended interrupt vector recording unit 19. The information stored in the selected extended interrupt vector is extracted and output.

Preferably, the interrupt polling unit 18 includes a selector 183 and a selection signal generator 183. The select signal generator 183 generates a select signal SEL for selecting one extended interrupt vector from the extended interrupt vector recorder 19 when an interrupt INTi is generated. The selector 181 selects one vector of the extended interrupt vector recording unit 19 by the selection signal SEL.

The shadow register 17 is a read-only register and stores address information of an interrupt processing routine which is output information of the interrupt polling unit 18. Preferably, the number of shadow registers 17 is less than or equal to the number of original interrupt vectors, and either vector of the extended interrupt vector recorder 19 is mapped to at least one shadow register 17.

The address remapping unit 13 receives the address information of the original interrupt vector 15 generated by the microprocessor 11, and replaces the address information of the shadow register 17 instead of the address information of the original interrupt vector 15. Occurs. Therefore, when the microprocessor 11 generates address information of the original interrupt vector 15 to refer to the original interrupt vector 15 in response to the generated interrupt request signal INT_REQ, the generated original interrupt vector 15 is generated. In response to the address information of "), the obtained information is information stored in the shadow register 17. " Preferably, the address remapping unit 13 replaces the shadow register in place of the address information of the original interrupt vector 15 only when a predetermined control signal SR_EN indicating that the shadow register 17 is being used is activated. Generates the address information of (17).

Also, preferably, the address remapping unit 13 is included in a device generally called a memory management unit (MMU). The memory management device manages a memory address for convenient access to the memory, and is a device that performs a function such as converting a logical address of the memory into a physical address.

2 is a flowchart illustrating an interrupt control method according to an exemplary embodiment of the present invention. Referring to this, the interrupt control method of the present invention is described as follows. In addition, the interrupt control method of this embodiment is applied to the interrupt control system of FIG. Therefore, for convenience of explanation, the reference numerals and reference numerals of FIG.

First, address information of interrupt processing routines is stored in each extended interrupt vector of the extended interrupt vector recording unit 19 (203). This process occurs mainly during the initialization of the system, i.e. when the microprocessor boots. The microprocessor 11 generates the address of the original interrupt vector 15 (205). This process occurs when the microprocessor 11 receives the interrupt processing request signal INT_REQ. When the address of the original interrupt vector 15 is generated, the address remapping unit 13 generates address information of the shadow register 17 in place of the address information of the original interrupt 15 (207). Then, the interrupt processing routine indicated by the address information stored in the shadow register 17 is allocated and the interrupt is processed (209). However, before the last step 209, by the interrupt polling unit 18, any interrupt among unprocessed interrupts is selected, and address information of the interrupt processing routine corresponding to the selected interrupt is received from the extended interrupt vector unit 19. It is extracted and stored in the shadow register 17.

FIG. 3 is a diagram illustrating an interrupt process according to the interrupt control method of FIG. 2 and an interrupt process according to a conventional software polling method. Referring to this, when an interrupt occurs, the process of reaching the desired interrupt processing routine according to the interrupt control method of the present invention will be described in comparison with the process of reaching the same interrupt processing routine according to the conventional software polling method.

Steps 11 to 13 are based on software polling. First, in step 11, when the interrupt processing request signal INT_REQ is generated, the microprocessor refers to the original interrupt vector. The original interrupt vector contains address information that points to the software interrupt polling routine. Thus, the process branches to a software interrupt processing routine (step 12). In the software interrupt polling routine, one interrupt is selected among the generated interrupts according to whether or not the unprocessed interrupt is masked and priority. Then, to process the selected one interrupt, it branches to the corresponding interrupt processing routine (step 13). It is assumed here that the desired interrupt processing routine is the second interrupt processing routine. Therefore, two branches are passed after the interrupt processing request signal INT_REQ is generated.

On the other hand, processes 21 to 22 are according to the interrupt control method of the present invention. First, when the interrupt request signal INT_REQ is generated, the microprocessor tries to refer to the original interrupt vector. However, what is actually referenced is the shadow register, not the original interrupt vector. The shadow register contains address information of the second interrupt handling routine, which is one of the interrupt handling routines by hardware polling. Thus, the branch to the desired interrupt handling routine immediately after referencing the shadow register.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

By the interrupt control system of the present invention, interrupts generated from a greater number of interrupt sources than the interrupt sources corresponding to the interrupt vector regions provided by the microprocessor can be processed quickly.

Claims (5)

When a predetermined interrupt processing request signal is generated, the microprocessor generates address information of a predetermined original interrupt vector and allocates the corresponding interrupt processing routine among a plurality of interrupt processing routines according to the information corresponding to the address information. To An extended interrupt vector recording unit for recording address information of the plurality of interrupt processing routines, the extended interrupt vector recording unit comprising a plurality of vectors storing address information of each interrupt processing routine; An interrupt polling unit for selecting any one of the unprocessed interrupts according to a predetermined rule and extracting and outputting address information of an interrupt processing routine corresponding to the selected interrupt from the extended interrupt vector recording unit; A shadow register for storing output information of the interrupt polling unit; And And an address remapping unit configured to receive the address information of the original interrupt vector generated by the microprocessor and generate address information of the shadow register in place of the address information of the original interrupt vector. The method of claim 1, wherein the address remapping unit And in response to the activation of a predetermined control signal indicating that the shadow register is in use, generating address information of the shadow register in place of the address information of the original interrupt vector. The method of claim 1, wherein the shadow register is Interrupt control system, characterized in that the read-only register. The method of claim 5, The number of shadow registers is less than or equal to the number of original interrupt vectors, And any vector of the extended interrupt vector recorder is mapped to at least one shadow register. In a method of controlling interrupts generated using an extended interrupt vector, A) storing address information of interrupt processing routines in the extended interrupt vector; B) generating address information of a predetermined original interrupt vector; C) the memory manager receiving address information of the original interrupt vector, and generating address information of a predetermined shadow register instead of the address information of the original interrupt vector; And D) assigning an interrupt processing routine indicated by the address information input to the shadow register, Before the step D), the shadow register is input with the address information of any one of the address information of the interrupt processing routine stored in the extended interrupt vector according to an unprocessed interrupt. Interrupt control method.