JPS6318439A - Information processor - Google Patents

Abstract

PURPOSE:To effectively utilize a large-capacity register suitable for an object to be processed, by matching the interface of an internal register file selecting signal line to the interface of a memory selecting signal line. CONSTITUTION:When an external interruption signal 13 is inputted to an infor mation processor 31, an up-down counter 14 is counted-up by '1' and a register file address 2 is increased by '1'. Since the interruption input 13 is inputted to the interruption input 14 of the processor 31 through a timing circuit when the signal 13 is inputted, the register file which is selected before the interrup tion input is inputted changes to a new register file together with the interrup tion input when it is viewed from the processor 31 side and the process is contin ued. Moreover, when a memory address 5 which is determined by a decoder 41 is accessed by the processor 31, a signal is inputted to the countdown input of the counter 14 and the address 2 is decreased by '1', and then the register file before the interruption signal is inputted is again selected. Therefore, the saving and restoration of a register can be made equal to those realized by accessing the memory address.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing system that realizes external selection of an internal large-capacity register file, and particularly relates to an information processing system that realizes external selection of an internal large-capacity register file.
The present invention relates to an information processing system suitable for Tsusa.

[Conventional technology]

Conventional equipment is 1 e.g.
trnction SetComputer Arch
items for VLSI Manoli
s G,f(,1(atevenis 'l'heM
As discussed in ITpress), much consideration has been given to register file selection methods at the architectural design level. However, the CPU
Regarding the register file selection method at the circuit design level using , there was no arrangement.

[Problem that the invention seeks to solve]

In the above conventional technology, the method of reusing large capacity registers is limited not at the architecture design level of the information processing unit (CPU) but at the circuit design level using the CPU.
If a PU user wants to realize a method of using large-capacity registers that is suitable for him or her, there is no consideration given to the CPU architecture design, which means that the uses of large-capacity registers are limited. was there.

The purpose of the present invention is to realize a CPU architecture that allows CPU users to use large-capacity registers, which are being realized due to advances in semiconductor technology, by using external circuits. Means] The above object is achieved by using the number of a register file constituting a large-capacity register inside the CPU as an address, and making the address selectable from outside the CPU in the same way as a memory. To enable selection from outside the CPU,
The address line for selecting the register file uses the same interface as the address line for memory selection.

The selected register file is Onchitsu7'R.
, AM does not mean ``M'', but rather a set of registers that have the functions of an accumulator, index register, or general register. Therefore, the present invention provides a plurality of register sets, and selects each register set by considering each as a register file.
It can also be applied to U (68000°8086 etc.).

Registers that are once selected and then deselected retain the previously written values.

[Effect]

By matching the register file selection interface to the memory selection interface, all peripheral devices used for memory selection can be used for register file selection.

The register file address line allows the selected register file to function as a register and hold the data written when it is not selected, so register set selection, save and restore can be performed externally (from your own CPU). (including memory selection address lines).

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. A register file 1 constituting a large-capacity register group has a plurality of registers 3, and a register file address decoder 4.
selected by The register file address decoder 4 decodes the signal of the register file address 2 inputted from the outside of the information processing device 31, and makes the selection signal 7 of the register file to be selected valid. The register file address decoder 4 is set so that the register file address 2 signal operates at the same voltage level and timing as the signal 5 that determines the memory address. The signal input to register file address 2 becomes valid,
What is the timing at which the register file to be selected is linked with the arithmetic unit 8?

This is the time when the register file decoder selection signal 6 becomes valid.

The data set in the register 3 in the register file 1 is retained even when the register file is deselected, and when the register file is selected again, the contents before the deselection become effective.

Using the information processing device 11 with the above-described configuration, an example of an external circuit for setting a device with one set of registers will be explained using the second example.Register file address 1
Make sure that only one of the 8 signal lines is always valid,
Other signal lines are set to be invalid. The register file decoder selection signal 17 is also set to be always valid. In this example, the present invention shows that the conventional register set is
This shows that there is no obstacle to realizing a set of information processing devices.

An embodiment of an external circuit for allocating register file addresses to the lower 16 addresses of memory addresses using the present invention will be described with reference to FIG.

Lower 16 addresses of memory address 5 (from AO to A3)
is connected from register file address 2 RO to AR3 through a timing circuit 11 for synchronization.

The upper address (A4 to λm) of memory address 5 is connected to an upper address decoder, and the decoding result is connected to register file decoder selection signal 6. 1 from the memory address determined by the upper address decoder 12 by this circuit.
The 6th address corresponds to the register file address, and the register file can be selected in the same way as memory.

A method of saving and restoring a register when an external interrupt occurs is performed by hardware using the present invention and an external circuit will be described with reference to FIG. The output of the up-down counter 14 is connected to the register file address 2, and an external interrupt signal and a signal obtained by decoding the memory address of the information processing device are input to the count-up input and count-down input of the up-down counter 14, respectively. Furthermore, the external interrupt signal 13 is connected to the register file decoder selection signal 6 and the interrupt signal 15 of the information processing device through a timing circuit. When an external interrupt signal is input to this circuit, first, the up/down counter 14 counts up by one, and the register file address 2 increases by one. At this point, the timed interrupt input enters the interrupt input 15 of the information processing device, so from the information processing device's perspective, the register file that was selected before the interrupt input changes to a new register file with the 1 interrupt input. Processing will continue.

Also, the memory address 5 determined by the decoder 41
When accessed by the information processing device, a signal is input to the countdown input of the up/down counter, and register file address 2 is decremented by one. This means that the register file before the interrupt signal was input is selected again.

The operation described above is equivalent to automatically saving the register at the same time as the interrupt signal is input, and restoring the register by accessing the memory address determined by the decoder 41. This operation is a register save by software.

It is very fast compared to recovery.

〔Effect of the invention〕

According to the present invention, the external circuit is connected to the information processing device t (C
PU) Select and save internal register file.

The recovery method can be determined by the CPU user, and many functions (counters, decoders, (timer, etc.) can be applied to register file selection, which has the effect of making it possible to effectively utilize large-capacity registers suitable for the processing target.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram for explaining the entire embodiment of the present invention, FIG. 2 is a block diagram for explaining that the present invention does not impede the functions of a conventional information processing device, and FIG. FIG. 3 is a block diagram showing a method of memory mapping internal registers using the present invention, and FIG. 4 is a block diagram showing a method of efficiently processing when an external interrupt occurs using the present invention. . 1... Register file, 2... Register file address, 3... Register, 4... Register file address decoder, 5... Memory address, 6...
- Register file decoder selection signal, 31... Information processing device, 11... Timing circuit.

Claims (1)

[Claims] 1. In an information processing device having an instruction execution device and memory having a large-capacity register group consisting of a plurality of register files and an arithmetic means, the register file used for instruction execution is stored outside the instruction execution device. An information processing device characterized by being selectable. 2. An information processing device according to item 1, wherein the register file can be externally selected by adding an external circuit to the information processing device. 3. An information processing apparatus according to item 2, wherein the method for externally selecting the register file is the same as the method for externally selecting the memory. 4. In the information processing device described in item 2, by selecting a register file using an external interrupt signal as an additional external circuit, it is possible to perform register bank switching corresponding to high-speed register saving when an interrupt signal is generated. An information processing device characterized by being provided with a mechanism for. 5. The information processing device according to item 2 is characterized in that a mechanism for selecting the register file to be used is provided by using a counter whose value increases in response to an external interrupt signal as an additional external circuit. Information processing equipment. 6. An information processing device according to any one of items 1 to 5, characterized in that the large-capacity register group and the calculation means are mounted on a single semiconductor chip.