JPH0324672A - Conversion circuit - Google Patents

Abstract

PURPOSE:To make it possible to apply the conversion circuit to wide video processing by connecting the output of a register to a light operation part and returning the output of the light operation part to the register at a prescribed timing. CONSTITUTION:A conversion part 30 connects the light operation part 32 to the branch of the output of the register 30 and returns the output of the light operation part 32 to the input side of the register 31. A selector 3 is connected to the input of the register 31 and the output of the light operation part 32 is inputted to the selector 33. Data D1 are inputted to the address input of the register 31. The selector 33 alternatively leads the output of the light operation part 32 and data D2. Since the data through the light operation part 32 are returned to the input side of the register 32, various processing such as the repeat of the same arithmetic processing and the integration, gradual reduction and sequential comparison of data can be attained. In addition, the circuit can be also used as a table for applying an address to the register 31 by the data D1 and reading out data stored in the address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a conversion circuit, and particularly to a conversion circuit that is effective for real-time video processing and display, real-time image analysis, etc. in a digital video processing system. [Prior Art] Conventionally, for example, in image processing systems that recognize images based on features extracted from input images, digital processing has been used due to the sophistication, reproducibility, and quantitative nature of processing results, and the variety of processing. systems are often used. In this digital processing system, it is necessary to treat images as a collection of pixels, and the calculations related to pixels are enormous. For example, 512X512ii! In order to measure the particle size distribution for each 8-bit RGB pixel, the processing speed is 20 Mr.
Even if the calculation is performed using an ultra-large computer such as a PS, a processing time of several seconds is required, which is not fast enough for real-time processing. Therefore, a dedicated I for image processing
Although video processing has been made faster using C, the purpose of this dedicated IC is extremely narrow and cannot be used for a wide range of video processing. Therefore, when a video processing system is constructed using these dedicated ICs, the applications are limited and the cost performance is generally low.

[Problem to be solved by the invention]

The present invention was devised to solve these conventional problems, and provides a video processing system that can be applied to a wide range of video processing, is capable of faster processing than a general-purpose ultra-large computer, and has high cost performance. The purpose is to provide a conversion circuit for constructing.

[Means to solve the problem]

The conversion circuit according to the present invention includes a register, means for inputting data into the register, a light arithmetic unit connected to an output port of the register, and an output of the light arithmetic unit that returns the output to the register at a predetermined timing. It is characterized by having the means. [Example] The present invention will be explained below based on the illustrated example. In FIG. 2, the video processing system has an input section 10 into which pixel data is input, and the pixel data is sequentially processed in a calculation section 20 and a conversion section 30 from this input section 1O. In the calculation unit 20, calculation processing such as numerical calculation or state calculation is performed, and in the conversion unit 30, post-processing to obtain the final processed image and feature amount is performed. As shown in FIG. 3, pixel data P▲j is generally arranged sequentially for each scan line. In image processing, generally, as shown in FIG. 4, for example, 3×3 pixel data P(1-1>+ (j-1>, Pi,.

1〉, P (+..+ (j-11, P (i-1++
js P i. J. ．． P (Is11+ is P
(!-11.(j+1>, Pi+(j*1), P (
iol) + (j*1, is subjected to various processing.The size of this processing area is set to 2 x 2, or a larger area, and even a shape other than a square is set. It may also be a region.Normally, neighborhood processing is required to maintain such 3×3 and other regions, but in this embodiment, this neighborhood processing section is omitted.The pixel data is sent to the calculation section 20. The parameters necessary for image processing are calculated here.For example, the average density is one of these parameters, and can be calculated in the calculation section 20.

As shown in FIG. 5, the calculation section 20 includes a state calculation section 21 and a numerical calculation section 22. Condition bear calculation part 2! Then, the number of connections, an index of whether the pixel is a processing target, parameters T, F, D, and E for determining the Euler number, a convergence signal representing the state of the processed image and its vicinity, and others are calculated. be done. On the other hand, the numerical calculation unit 11 performs concentration averaging, first-order differentiation, second-order differentiation, filter processing, and other processing. The processing of these arithmetic units 2l and 22 is sped up by hardware-based pipeline processing.

FIG. 6 shows the configuration of the calculation section 20. Although the calculation section 20 is shown in detail in this figure, the state calculation section 2l is omitted. In the arithmetic unit 20, image data stored in one of the memories 41, 42, and 43 is transferred to a multiplexer (MUX) 49.
is selected and input. Each memory 41 42, 4
3 is connected to the multiplexer 49 and also to the integration unit 28 of the calculation unit 20 via buffers 51, 52, and 53.

That is, one of the memories 41, 42, 43 stores the input image, and the other memories store the input image.
2 and 53, the processing results of the calculation unit 20 are stored.

The calculation section 20 includes three flip-flops 23, 24, and 25 connected in series, a multiplication section 26, and a selector 27. The first flip-flop 23 stores pixel data Pjj@ along one scan line as shown in FIG.
It is input every l clock signal, is delayed by one clock, and is output to the second flip-flop 24 and the multiplier 26. The second flip-flop 24 delays the pixel data inputted from the first seven flip-flops 23 by l clocks and outputs the delayed pixel data to the third flip-flop 25 and the multiplier 26 . The third flip-flop 25 outputs the pixel data input from the second flip-flop 24 to the multiplier 26 after further delaying it by l clocks. Therefore, three consecutive pixel data are input to the multiplier 26 at the same time.

The multiplier 26 multiplies each pixel data by a proper numerical value, and outputs the calculation result to each input terminal of the selector 27. The selector 27 guides the multiplication results input to each input terminal to an arbitrary output terminal or distributes them to a plurality of arbitrary output terminals. The integrating unit 28 integrates the data of the operation results derived from the selector 27 while performing addition, subtraction, and other operations. The calculations within this integration unit 28 are performed hierarchically, and different calculations are performed simultaneously in each layer and passed to the next stage in a pipeline process, which improves the calculation speed of the entire calculation circuit. .

Now, as an example of the calculation content in the calculation unit 20, a calculation method for obtaining a Sobel operator in the y direction, which is one of the methods for emphasizing edges, will be described. This So
The bel operator calculates Δyfij =P (i-1)+ +i-+++2 Pt+ in the 3x3 convolution in Figure 4.
t=-n+P (▲+l1+ (j-1)( P
(i-1)+ (j*11 +2 P t+ (j4
11 + P li'l) + (j41+).

The pixel data stored in the memory 4l is read out sequentially, and the pixel data P(i-1>(j-th), P▲+(j-direct), P(!*+1.(j-1) They are simultaneously transferred from the flip-flops 25, 24, and 23 to the multiplication unit 26, and multiplied by l, 2, and l, respectively.Then, the integration unit 2
8, P (r-+h(=-u + 2 P t・lj- 1
1 + P (i·-++ +j-11 is calculated, and this is stored in P i+ (j-11) of the memory 42.

Similarly, pixel data P (i-11
+ +jl)s P i+ (jugs P (i+l
)+ +j+I) are read, multiplied by (-1), (-2), and (-■), respectively, in the arithmetic unit 20, and the sum is stored in P i+ (j+l) of the memory 42.

Such processing is performed for one screen (512×512 pixels). Note that when storing data in the memory 42,
Unlike FIG. 3, the pixel data Pij is rearranged and arranged in the vertical direction.

Next, among the data read out from the memory 42, data PL. (j-11 and P i1j+ll are respectively transmitted from the flip-flops 25 and 23 to the integrating unit 28 via the multiplier 26
Once transferred to , these are summed, which gives the Sobel operator Δyf! in its 3×3 convolution. j is required.

The results of this processing are stored in Pi, (j-11) of the memory 43, and such processing is applied to all pixel data in one screen.

Other arithmetic operations such as smoothing or differentiation are performed in exactly the same manner.

The calculation results in the calculation unit 20 are stored in the memory 41,
42, 43, and then input to the converter 30 (FIG. 2) for final video processing, or for special video processing. l[t is found.

FIG. 1 shows a schematic configuration of an embodiment of a conversion circuit, that is, a conversion section 30 according to the present invention.

In this figure, the converter 30 connects a light arithmetic unit 32 to the branch of the output of the register 3l, and returns the output of the light arithmetic unit 32 to the manual input side of the register 31. A selector 33 is connected to the input of the register 31, and the output of the light arithmetic unit 32 is inputted to this selector 33. Data D1 is input to the address input of the register 3l, and the output terminal of the selector 33 is connected to the data input of the register 3l. The selector 33 receives data D2 in parallel with the output of the light arithmetic unit 32.
is input, and the selector 33 selectively guides the output of the light arithmetic unit 32 or the data D2 to the register 31.

By returning the data that has passed through the light arithmetic unit 32 to the manual side of the register 31, it is possible to repeatedly perform the same arithmetic processing on one piece of data, or to perform the same processing on a series of data groups and then sequentially store them in the register 31. It is also possible to
In addition, extremely diverse processing such as data integration, data gradual reduction, and data successive comparison becomes possible. Also, register 31
It is also possible to use it as a table by giving an address to the table using data DI and reading out the data stored at that address.

As the light arithmetic unit 32, for example, an adder can be adopted. In this case, data D3 is input to the light arithmetic unit 32, that is, the adder, in addition to the output of the register 31, and the register 31 also receives CS (chip select) or W
E (write enable) signal S is input. For example, when calculating the area in a binary image or a labeled image, specify the pixel value as the address DI, output the data stored in that address from the register 3l,
The adder 32 adds D3 (here set to "1") to this data and returns the value to the selector 33 and stores it again at address D1 of the register 3l. As a result, the number of pixels of each pixel value in the image is counted, and the area of each label area is determined.

FIG. 7 shows the structure of the register 3l in detail.

In this embodiment, the register 3l is configured to be able to hold, for example, 16 bits of IK data. That is, a circuit 34 consisting of a multiplexer 35, 1000 flip-flops 36, and a selector 37
1-bit data is processed, and 16 such circuits 34 are provided in parallel. The selector 37 applies the clock signal CK only to the flip-flop 36 specified by the address signal D1, and the multiplexer 35 applies the clock signal CK to only the flip-flop 36 specified by the address signal D1. The output data (Q) of only the flip-flop 36 designated by is passed as data Do. Flip-flop 36 receives clock signal C
The input data DI is held by inputting K,
Output the retained data as output data (Q). This makes it possible to write and read 16-bit data by arbitrarily specifying the IK address. Switching between the write mode and the read mode can be performed, for example, by selecting whether or not to input the clock signal CK to the selector 37, and the circuit shown in FIG. 8 can be used. A write enable signal WT is used for switching between normal writing and continuous writing, but this write enable signal WT and a clock signal CK are manually input to the AND gate 7l. W here
I is low asserted, so invert and gate 7
It is input to l. When W1 becomes low level,
The ANDONI gate 71 now allows the CK to pass through, and the passed CK is manually input to the selector 37. The register 3l in FIG. 7 was an example in which an input port and an output port were provided separately, but if the register 31 has a single input/output port, an input port as shown in FIG. A circuit is provided for switching output ports. The aforementioned write enable signal n is also used for this switching.

The write enable signal W1 is inverted and input to the buffer 73 provided on the output line 72, and
The data is directly input manually to the buffer 75 provided in 4. That is, when the lower write enable signal W is rLOWJ,
The buffer 73 becomes high impedance and the data D
can now pass through Bazza 75 as data DI, thereby performing data input to the register. In contrast, the write enable signal W”
When llm is rHIGHJ, the buffer 75 becomes high impedance, and the data DO passes through the buffer 73 and comes out as output data D. This causes data to be output from the register. Thus, the input/output ports are switched, and data input and data output are selectively performed.

The light operations of the converter 30 include addition, subtraction, maximum and minimum value extraction, numerical operations such as absolute values, comparison, AND, OR, NAND, NORSEX-OR, E
Logical operations such as X-NOH can be freely selected and adopted.

Furthermore, since the converter 30 is equipped with a register 31, it can be used as a lookup table for data reference such as referring to RGB values from a so-called color code, or when labeling an image, it can store labeling information at high speed. Needless to say, it can be applied as a cache memory.

FIG. 9 shows another example of the video processing system. In this embodiment, a plurality of input units IO and image memory 40 can be selected by a selector 6l as a human power unit,
Furthermore, a plurality of output sections 62 and the image memory 40 can be selected by a distributor 63 as output sections. Examples of the input unit 10 include a VTR camera, scanner, video deck, laser disk device, CD-ROM, optical disk, hard disk, communication 1/F, and image memory. On the other hand, the output section includes those listed as the input section that can accept data, and an image memory.

Furthermore, in this embodiment, the calculation unit 20, the conversion unit 301, the selector 61, the distributor 63, the distributor 63, and the image memory 40
A controller 64 is connected to the controller 64, and settings and control are performed by the controller 64. Overall control and setting and control of the controller 64 are performed by the MPU 65. Further, complicated calculations in video processing are performed by the MPU 65. This is because if the load on the calculation section 20 or the conversion section 30 is too high, the calculation speed will drop significantly, and the processing allocation should be optimized depending on the processing content.

In the video processing systems shown in FIGS. 2 and 9, neighborhood processing of 3×3 pixel data (FIG. 4) is performed by the calculation unit 2.
0, but instead of this, a neighborhood processing section that outputs 3x3 pixel data simultaneously may be provided. Further, in each of the above embodiments, the calculation unit 20 has been described as processing pixel data, but is not limited to pixel data, and the present invention can be applied to all digital data processing systems.

〔Effect of the invention〕

As described above, the present invention can be applied to a wide range of video processing, and can perform processing faster than general-purpose ultra-large computers.
Furthermore, it is possible to obtain a conversion circuit for constructing a video processing system with high cost performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a conversion circuit according to the present invention, FIG. 2 is a block diagram showing an example of a video processing system, FIG. 3 is a conceptual diagram showing an arrangement of pixel data, and FIG. 4 is a block diagram showing an example of a video processing system. 3×
3 is a conceptual diagram showing the arrangement of pixel data, FIG. 5 is a block diagram showing the concept of the calculation section, FIG. 6 is a block diagram showing an example of the calculation section, FIG. 7 is a circuit diagram showing the register, and FIG. 8 9 is a diagram showing a register input/output port switching circuit, and FIG. 9 is a block diagram showing another example of the video processing system. 30... Conversion unit 31... Register 32... Light operation unit

Claims (1)

[Claims] (1) A register, a means for inputting data into the register, a light arithmetic unit connected to an output port of the register, and a means for returning the output of the light arithmetic unit to the register at a predetermined timing. A conversion circuit characterized by: