GB2129589A - Array processor cell - Google Patents

Abstract

An 8-bit array processor cell is described having input registers (N1 to N8) and an output register (N0) for input/output connection to other cells in an array, arithmetic and Boolean processing means (P), control means (CR), and direction- indicating means (62). The control means may be capable of storing information and causing the cell to convert data in a plurality of different ways. The processing means may be connected to modify information stored by the control means allowing a cell to react according to inputs received from neighbouring cells. The direction-indicating means indicates which neighbouring cell provided data being processed so that a cell in a three-by-three array portion having a certain value in relation to the other cells in the portion can be identified. Processor arrays using such cells are also described. <IMAGE>

Description

SPECIFICATION Array processor cell The present invention relates to a cell containing an arithmetic and logic unit (ALU) and associated registers for carrying out arithmetic and Boolean functions on data which relates to the cell itself and to neighbouring cells in an array. A plurality of cells arranged in an array may be used for processing images and in such an array each cell may correspond to a picture element in the image, or the array may be scanned over the image so that at any time each processor corresponds to a picture element of part of the image.

A previous image processing system for binary data, the CLIP 4 system, is described in a paper "Review of the CLIP imaging system" by M.J.B. Duff, National Computer Conference, 1978, where the array comprises 96 by 96 CLIP 4 cells. Each cell has a processor which is controlled to carry out various functions by control signals applied to external terminals. Further information on CLIP systems and the ways in which they can be operated will be found in a paper "Towards CLIP 6 an extra dimension" by T.J. Fountain, IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, Hot Springs, Virgina, November 11 to 13, 1981, pages 25 to 30. The references of these papers give examples of arrays of processor cells and of the ways in which they can be operated.

According to the present invention there is provided a processor cell for use in an array of such cells, comprising at least eight input terminals, each for receiving data from a respective cell in an array of cells, an input/output port for reading data from a central source for the array into, and out of, storage, processing means for processing the data received by way of the input terminals and the port, multiplexer means for allowing the processing means to access independently data received by way of the respective input terminals, an output terminal for connection to input terminals of other cells, the processing means being coupled to the output terminal to pass processed data thereto, control means for receiving and storing information for controlling the cell at least partially in accordance with the information so stored, and directionindicating means for indicating by way of which input terminal data used by the processing means reached the cell.

An advantage of the invention is that the direction-indicating means may indicate which neighbouring cell provided data being processed, or which has just been processed, so that for example the cell having the maximum or median value in a three cell by three cell portion of an array can be identified. If provision is made for the processor to modify the directional indication by, for example, adding a number which represents rotation through an angle, processing can be propagated in directions which depend on data received by a cell from neighbouring cells.

A further feature which is preferably included in a cell according to the invention is that the control means is capable of causing the cell to convert data in a plurality of different ways and thus different cells in an array can be controlled internally using the control means to carry out simultaneously a plurality of different processing functions.

The processing means may be connected to be capable of modifying information stored by the control means. An advantage is then obtained that cells can react according to inputs received from neighbouring cells.

Unlike previous array processor cells, the cell according to the invention is preferably capable of handling inputs from other cells and data from the central source in 8-bit bytes and of processing such bytes. Thus the advantage is obtained that images represented in grey levels can be processed.

Preferably data is read simultaneously from neighbouring cells, by way of the input terminals, into respective input registers, one for each input terminal, the data passing serially into the input registers. Multiplexing may then be provided to allow the contents of any selected input register to be applied to the processor.

Additionally a binary gate may be provided with each gate input coupled to a respective input terminal of the cell and the gate output connected to the processor input. The provision of parallel control for the gate inputs then allows binary data to be passed to the processor more quickly than 8-bit data. Time saving achieved in this way is important because many array processing procedures aim to simplify 8-bit data and often many cycles near the end of processing are carried out with binary data.

Each cell preferably has its own random access memory (RAM) which is conveniently coupled to the cell by means of further port but the RAM may be part of the same integrated circuit as the remainder of the cell.

Arrays of cells according to the invention may, for example, be single instruction multiple data arrays, in which each cell receives the same instruction word; or multiple instruction multiple data arrays, in which cells, or groups of cells receive respective instructions; or pyramid arrays in which output terminals of a group of cells in each level, except the top level, supply outputs to cells in the next higher level, cells in each level being controlled by a single instruction word or by respective different words.

Certain embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a portion of an array of cells each according to the invention, showing data paths to the central cell shown, Figure 2 is a block diagram of an integrated circuit of a cell according to the invention, showing data paths, Figure 3 is a block diagram showing the input matrix of Fig. 2 in more detail, Figure 4 is a block diagram showing the control connections of the cell of Fig. 2, and Figure 5 shows stages in finding the median value of values held by cells in the part array of Fig. 1.

The portion shown in Fig. 1 of a much larger array comprises nine processor cells 1 to 9.

Each cell has eight 8-bit input shift registers as indicated by the designations N1 to N8 for the cell 9 and one 8-bit output register designated No for the cell 9. In Fig. 1 only that one of the input registers connected to the cell 9 is shown in each of the cells 1 to 8 but in each of these cells the output register is shown. Only the data paths inter-connecting the cell 9 with its surrounding cells 1 to 8 are shown but every other cell in the array is connected in the same way in relation to its surrounding cells, connections being omitted where cells are adjacent to the edge of the array. Control connections not shown in Fig. 1 are also required as are further data paths for loading the array and indicating the results of processing. These further connections and paths are described later.

The data paths within the cell 9 are shown in Fig. 2. The registers Nl to N8 are connected to an input matrix 12 which together with eight groups of gates MO to M7 allow the contents of each register to be read separately on to the lower significance portion 1 3L of a 1 6-bit bus 13.

The cell 9 comprises a 1 6-bit ALU P, a 16-bit register and bidirectional shifter S and a block BR of four 16-bit registers, sixteen bits being required to handle arithmetic operations on 8-bit bytes. The ALU P, the register S and the block BR are interconnected by the bus 13 and additional 1 6-bit buses 14 to 17 to form a loop to crarry out Boolean and arithmetical operations examples of which are given later. Each bus is divided into higher and lower significance portions designated by subscripts H and L.

The ALU P is connected to a RAM port 18 and from thence to a RAM 20 typically both in a separate integrated circuit specific to the cell concerned and having storage for 2K bytes.

Data concerning an image to be processed is passed to a dual input/output register D connected to input and output ports 10 and 11 so that information to be stored can be passed to the RAM 20 either direct or by way of the processor P. Results of processing are read from the RAM by way of the output port. The 8-bit input port 10 is parallel connected to the output port of the previous cell in the array and the output port 11 is parallel connected to the input port of the next cell in the array. Thus input and output to the cells is by shifting through D registers until the required cell is reached.

Each cell has a condition register CR which is used to control the operation of the cell by means of connections shown in Fig. 4 but is also in a data path formed by buses 21 and 22 and the bus 14. Thus when the cell is under the control of the register CR its operations may depend on processing carried out by the cell itself. Since the register CR has a control function a separate tri-state buffer 23 is provided to gate the output of the register CR to the ALU P only when required while allowing control functions to be applied to various parts of the circuit.

An object of processing 8-bit data is to simplify the data to binary form and in order to speed operation when this state has been reached, or if the initial data is in binary form, a binary gate BG is connected to the input matrix to apply binary bits as the least significant bit on the bus 13.

In Fig. 3 where the input matrix is shown in more detail, a group 24 of eight input terminals for receiving inputs from neighbouring cells are connected to the registers N1 to Na, respectively, (only the outline of the register N, being shown). The eight internal stages of this register are designated 31 to 38 and it can be seen that the other registers are connected in the same way to respective input terminals in the group 24. Each of the groups of gates MO to M7 is connected to a stage of corresponding significance in each of the shift registers N1 to N8 so that by applying a 3-bit signal to the groups of gates, the contents of any of the registers N1 to N8 is gated to the bus 13.

The binary gate BG is connected to the input terminals 24 and includes a group of AND gates 40 and an OR gate 41. Each AND gate receives one input from one of the terminals 24 and one from the control register CR so that a binary input from a neighbouring cell can be steered to the least significant part of the bus 13.

The input matrix and gating shown in Fig. 3 has particular advantage in the present application since it enables the number of pins or each integrated circuit to be reduced to 64, and it is convenient for the type of bus structure typically used for an ALU or microprocessor.

The control logic for the cell of Fig. 2 is now described in connection with Fig. 4. A number of external terminals will be mentioned and for a single instruction multiple data array these terminals are connected in parallel to all cells in the array. Control signals, usually in the form of operation codes furnished by a central system controller usually a computer, are applied to the external terminals to cause processing to take place. For multiple instruction arrays means are provided for addressing the external terminals of each cell, or of groups of cells, individually.

Loading the registers BR, S, CR and No and a register in the port D is carried out on the application of respective pulses to external terminals 42 to 46. Eight pulses, equivalent to clock pulses, are required to shift data into the registers N, to N8 and, at the same time, out of the register Not these pulses being applied at a terminal 47.

If the cell is to be under internal control a number of operations are enabled by the application of a control pulse to a terminal 48. These operations are applying a control signal to the ALU; loading the register S, the control pulse being applied by way of gates 92 and 93; loading the register CR, control being by way of gates 95 and 96; loading the output register Not control being by way of gates 97 and enabling either gates 65 or gates 66 (connected via an inverter 94), allowing addressing of the block BR of registers from external terminals 67 and 68 or from the register CR.

When the cell is under internal control the gates 92, 93 and 95 to 98 are controlled by the "condition" bit in the register CR which appears at a terminal 49 of that register, enabling loading of the registers S, CR and No The ALU P is controlled by way of five terminals 50 to 54, these terminals also being connected by way of a decoder 55 to control the register S. Two further outputs from the decoder 55 are used to set the state of a flip-flop 56 which in one state enables gates 57 so that external terminals 59 to 61 can be used to control the gates MO to M7 (see Fig. 3) and load a multiplexer direction register (MDR) 62, while in the other state gates 100 are enabled passing control of the gates MO to M7 and the register 62 to the register CR.

Of the 32 possible 5-bit binary signals applied at the terminals 50 to 54, sixteen specify different Boolean operations and eight specify four different add operations and four different subtract operations, the differences being whether the negative, carry, zero or overflow outputs of the ALU are set. Of the remaining eight 5-bit binary signals, four set the S register mode to either logical rotate, arithmetical shift, logical shift or parallel input, two control the direction register 62, and one causes the direction register to output to the ALU.

In some operations it is necessary to clear selected input registers Nl to N8 and this is the function of a decoder 63 under the control of the direction register 62 and on command from an external terminal 64.

In addition to the register S input data for the processor P may be provided from four sources: the registers BR, the tri-state buffer 23, the gates MO to M7 or the binary gate BG, selection being under the control of a decoder 70 having external input terminals 71 and 72.

Data selection for input to the registers S, D, CR and No is also from four sources: the RAM 20, the register D, the data outputs of the ALU and bits which provide additional information as to the result of the process controlled by signals at the terminals 50 to 54; that is carry and "round-up" bits, a condition bit and the zero bit of the register S, these four bits reaching the bus 15, by way of a channel 15'. Apart from the RAM 20 which is accessed conventionally by the central system controller, these sources are controlled by a decoder 73 with external input terminals 74 and 75.

The carry input for the processor is selected from 0, 1, the round-up bit or the carry bit using a decoder 86 with external input terminals 87 to 88, these bits being selected as required for different operations and supplied by way of lines 104, 105 (connected to the supply voltage SV), 83 and 84. Selection of shift direction for the register S is by means of external terminal 90 and timing is controlled from an external terminal 101. The input to the register D is selected from the bus 10 or the bus 15, by means of an external terminal 91.

The condition register CR for internal control has the bit assignments given in Table 1. TABLE 1 Register Bit Assignment 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Multiplexer direction select Binary gate direction field B-register address S-register bit 0 ALU bit 2 (R) ALU carry output N/A N/A Conditional load Bit 15 "conditional load", appearing at the terminal 49, is selected from the carry, negative (that is an indication of a negative result), zero (that is an indication of a zero result) and overflow from the processor on lines 76 to 79 respectively. Selection is made, as is mentioned above, by means of signals applied to the processor function external terminals 50 to 54 applied to a decoder 102.The register CR also receives the carry bit direct from the processor together with the round-up bit and the S register bit 0 by way of connections 76, 81 and 82 respectively. On the output side of the CR register the carry, round-up and add bits are passed to the processor by way of the lines 83 and 84, and a line 85, respectively. The S register bit 0 determines, by means of the ADD bit on the line 85, whether the ALU adds two applied inputs (from the registers BR and S) or passes one input without such addition.

The pervading influence of the register CR will now be clear. In the broadest terms cell operation is as follows: (1) The result of one cycle of cell operation is stored in the condition code register CR.

(2) The stored condition determines the cell operation during a second cycle.

Table 1 and Fig. 4 show that the outputs of the register can influence the following areas of cell operation: (1) The loading of S, C and No registers (bit 15) (2) The multiplexer direction (bits 0-2) (3) The binary gate directions (bits 0-7) (4) The BR register address (bits 8 and 9) (5) The ALU carry input (bits 11 and 12) (6) The ALU function (bit 10) The input to bit 15 is chosen from amongst the Carry, Zero, Overflow and Sign outputs of the ALU by means of decoder 102 and the ALU operation code during arithmetic operations.

Since, as has been mentioned, the register CR is positioned on the data path of the cell (see Fig. 2), its contents may themselves be manipulated by the ALU and shifter to give many modes of operation.

Finally in relation to the influence of this register on cell operations, the external microcode (see Table 2 below) contains one bit 12 applied at the terminal 48 which permits the outputs of the register to be used or ignored, thus differentiating between conditional and unconditional cell operation.

TABLE 2 External Microcontrol Bit Assignments Terminals 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

59 MUX direction select 60 61 74 Input node source 75 42 B register control 67 68 43 S register control 90 101 C register control 44 48 50 51 52 Processor control 53 54 87 88 74 Data node source 75 Conditional clear 64 Input Registers 46 D register control 91 45 Propagation control 47 The circuit of Figs. 2, 3 and 4 can operate on binary or multivalue data and although for the former additional circuit functions may be invoked which will be described later, generally operations on the two types of data are indistinguishable.Accordingly, some typical circuit operations which are now given are described in terms of multi-valued data and binary operations are the one-bit case of the multi-bit operations, except where stated.

Data for the cell is usually loaded to and from the cell by way of the register D. When data is input to the cell it is most usually loaded from the register D to the RAM 20 via the bus 15, but it may be moved to the registers S, CR or N0. Either the RAM or the processor outputs may be the source of data shifted to the register D for output. For both input and output, loading (except from the RAM) is under the control of the decoder 73.

In "pointwise operation" the result is a function of two inputs already resident in the cell, typically in the RAM. A simple function of this type is the addition of two numbers when the result is known to be less that 8-bits. This operation is summarised by the four steps: 1. RAM to S 2. RAM to S and S to BO 3. ALU = BO plus S 4. ALU outputs to RAM In the first step the first operand is loaded from the RAM 20 into the register S and at the second step the contents of the register S is shifted to that register in the block BR which has the address 0 while the second operand is loaded from the RAM 20 into the register S. At the third step the processor P performs the addition and in the fourth step its output is loaded to the RAM 20.

Another example of an arithmetic operation (multiplication) is now outlined: 1. RAM to S 2. RAM to S and S to BO 3. ALU = BO plus S 4. ALU outputs to RAM 5. RAM to S 6. S to BO and RAM to S 7. Bit SO to C10 8. S to B2 9. ALU=BO 10. ALU outputs to S 11. ALU = B1 plus S or B1 1 2. ALU outputs to S 13. Sto B1 14. ALU = B2 15. ALU outputs to S 16. Shift S down 17. Bit SO to C10 and S to B2 18. ALU = BO 19. ALU outputs to S 20. Shifts S up 21. Sto BO 22. ALU = B1 plus S or B1 23. ALU outputs to S 24. Repeat 1 3 to 23 to 100. seven times 101. ALU=S 102. ALU outputs to RAM 103. Shift S 8-bits down 104. ALU = S 105.ALU outputs to RAM In this operation two floating point numbers each comprising an 8-bit exponent and an 8-bit mantissa are multiplied. In the first four steps the mantissas are added and in the remaining operations one exponent is held in the S register while the other exponent is held in register BO of the group BR. At each stage in multiplication a different bit of the multiplier (held in the register B2) is transferred by shifting down in the register S to bit 10 of the register CR (steps 14 to 17). Bit 10 then determines whether the multiplicand (held in the register BO) is added (steps 13, 22 and 23), after being shifted up (steps 18 to 21) to a number at address B1 where the product is accumulated.Steps 5 to 13 load the registers BO, B1 and B2 to carry out the first stage of this process, steps 101 and 102 pass the low order byte of the product to the RAM 20, and steps 103 to 105 pass the high order byte of the product to the RAM 20.

Although both the examples given above are of arithmetic functions any Boolean function of two variables may also be formed by the ALU. As has been mentioned, signals applied to the terminals 50 to 54 determine the type of operation carried òut.

"Neighbourhood operations" or "propagation operations'' are, of course, important operations in arrays of cells and consist of deriving a result which is a function of a value held by the cell and values held by its neighbours. The first step is usually to transfer a byte of data from the RAM 20 to the output register No and sometimes simultaneously to the register S. This step is carried out at the same time in all cells in the array and then data is transferred serially from each cell to its neighbours so that the contents of each output register No appears in one of the registers N, to N8 in every one of the neighbouring eight cells, data being transferred serially.

When the registers N1 to N8 have been loaded, the gates MO to M7 under the control of the decoder 70 and the gates 57 or the gates 100 pass signals to the ALU in sequence from the N registers. The ALU computes a new result each time an input is applied and this result is stored in the register S. Two examples of this process are now given.

The average value is computed by carrying out the following steps: 1. RAM to No 2. No to Ni (where i equals one to eight) 3. ALU = Ni 4. ALU outputs to S 5. ALU = Ni plus S 6. ALU outputs to S 7.

to Repeat 5 and 6 six times 18.

19. ALU bit 2 to C11 20. Shifts S 3 bits down 21. ALU = S plus C11 22. ALU outputs to RAM The first two steps load the registers N, to N8 and in the third step the "first direction" corresponding to the register N1 is selected and the value of N1 is shifted by way of the ALU to the register S (steps 3 and 4). In step 5 the ALU adds the contents of the next input register to that of the register S and transfers the result to the register S. In operations 7 to 18 previous operations 5 and 6 are repeated six times so that the total of the contents of the eight input registers N1 to N8 is accumulated in the register S. In the operation 19 the ALU bit 2 is transferred to control register position 11 and in operation 20 the contents of the register S are shifted down by three places thus dividing by eight to form the average.In the operation 21 the contents of the S register are added to the bit in CR register position 11 to round-up the average held in the S register and following this operation the contents of the ALU are moved to the RAM 20 in operation 22.

To compute the maximum value of a three by three neighbourhood the procedure is as follows:~ 1. RAM to S and Nout 2. Nout to Nin 3. ALU = S minus Nin 4. Negative bit to C15 5. ALU=Nin 6. Conditionally load S and MDR 7.

to Repeat 3 to 6 seven times 34.

35. ALU = S 36. ALU outputs to RAM In the first step the appropriate value for the cell 9 itself is transferred from the RAM 20 to the register S and in addition in steps 1 and 2 the input registers of the cell are loaded. In step 3 the ALU P calculates the value of the contents of the S register minus the contents of the register N, and if a negative occurs indicating that the contents of N, are greater than the contents of the register S, the negative bit resulting in the ALU is transferred to bit 15 of the control register CR. In step 5 the ALU is loaded with the contents of the N1 register so that in step 6 if bit 15 of the control register is set the contents of the ALU are loaded into the register S. Additionally the current input register address held by the control register CR is conditionally loaded into the direction register (MDR)62.By repeating steps 3 to 6 seven times the maximum value of the neighbourhood is held in the register S where it can be transferred by way of the ALU to RAM in operations 35 and 36. Also the input register address of the maximum value is available in the direction register 62.

The cell 9 also has the important property of being able to manipulate data which represents directional information rather than a numerical value.

In one aspect of directional information operations, the condition code register CR is able to control the gates MO to M7 or the binary gate and since the CR register is in the processor loop control information for direction selection can be manipulated as data. For example if a maximum is found to be in one particular direction, say the direction of the processor 3 in Fig.

1, then the opposite direction of the processor 7 can be selected by adding four to the direction held by the multiplexer direction register 62, the result being passed to the register CR to control the gates MO to M7. As is indicated in Fig. 2 the contents of the multiplexer direction register 62 are available to the data path via the ALU using an operation code (including a signal from the terminals 48 or 49) and a control connection 93. In this example the contents of register N7 can be selected for consideration to determine whether a line extends throught the array in the direction joining processors 3 and 7. If the register N7 holds a value near to that of the register N3, the direction 3 can be output via the RAM 20 and port D, and in the next cycle to the adjoining three-by-three portion of the array.

Alternatively, in processing a boundary in an image, if the cell 3 corresponds to a maximum value, the cells 2 and 4 can be examined by using the modified contents of the multiplexer direction register to examine cells 2 and 4. If the cells 2, 3 and 4 correspond to relatively high values the value corresponding to cell 9 can be modified.

These examples show how the operation of a cell can be made to be dependent on operations carried out by the cell.

The multiplexer direction register 62 also serves a purpose in computing the median value of a three by three neighbourhood. To find this value the maximum function as described above is performed for the neighbouring cells five times. On the first three occasions the input register containing the maximum value is cleared using the direction register 62, the decoder 63 and a clear signal applied at the terminal 64. Suppose the nine cells started with the values shown in Fig. 5a, the position is now as shown in Fig. 5b. On the fourth cycle the new maximum value is compared with the value for the cell itself.If the cell value is greater than the new maximum then the maximum is the required median value, this situation being shown in Fig. sub. if the new maximum value from the first four cycles and the cell value are equal then this value is the median, this situation being illustrated with starting values of Fig. 5c and the position after the first three cycles as shown in Fig. sod. if the cell value is lower than the new maximum found after four cycles then a fifth maximum operation is carried out on the remaining neighbours.A further comparison of the maximum found indicates the median if either the cell value is less than or equal to the maximum (see Figs. 5h to 5j) when the maximum value is the median or the cell value (see Figs. 5e to 5g) is greater when it is the median.

There are two special cases of circuit operation which are specific to binary data manipulation.

Firstly for storing binary data, it is inefficient to store only one bit of binary data per byte in the external RAM 20 which is-organised in bytes. Therefore closely packed binary storage may be used when special microcode sequences of shifting and masking are used.

Secondly many binary neighbourhood operations are facilitated by deriving composite Boolean functions of the neighbourhood input simultaneously. Binary gate BG allows this to be achieved and sequencing the gates MO to M7 is avoided saving time.

This description of the circuit is by no means exhaustive because the number of known modes is very large and because it is expected that new modes of operation will be discovered, perhaps by using a cell according to the invention in alternative machine architectures. However it will be clear from the above description how the cell can be operated in many useful ways and how it can be operated in conjunction with other cells in the array.

The invention may be put into practice in many other ways than that specifically described in connection with Figs. 1 to 4, for example each cell need not be constituted by a single integrated circuit or two such circuits if there is one RAM circuit for every cell. In functional partitioning, for example, the cell circuit is segmented into a process circuit comprising the ALU P and the registers S, CR and BR, and two multiplexer circuits each dealing with four bits of all neighbouring inputs. In an alternative, bit-slice partitioning, all the circuits appropriate to a limited number of bits are packaged in one unit and a number of such units comprise the final cell circuit.

In another arrangement each cell may include a read-only memory containing microcode for the control functions achieved by applying signals to most of the external connections.

Of course other arrangements of internal registers and buses may be used provided a condition register specific to, and for the control of, each cell is provided. In particular a microprocessor may be used.

Each connection from the output register of one cell to its eight neighbours may be replaced by eight connections to allow data to be transferred in parallel. The number of other cells in an array to which a cell is connected may be more or less than eight and the number of input terminals provided may be as required for a particular array construction.

Cells according to the invention may be connected as a relatively small array which is used to scan a relatively large array of picture elements or equivalent, the cell array processing portions of the large array in sequence.

Claims (14)

1. A processor cell for use in an array of such cells, comprising at least eight input terminals, each for receiving data from a respective cell in an array of cells, an input/output port for reading data from a central source for the array into, and out of, storage, processing means for processing the data received by way of the input terminals and the port, multiplexer means for allowing the processing means to access independently data received by way of the respective input terminals, an output terminal for connection to input terminals of other cells, the processing means being coupled to the output terminal to pass processed data thereto, control means for receiving and storing information for controlling the cell at least partially in accordance with the information so stored, and direction-indicating means for indicating by way of which input terminal data used by the processing means reached the cell.

2. A process cell according to Claim 1 wherein the direction-indicating means stores an identification of the input terminal by way of which the said data reached the cell, only on receipt of a control signal generated conditionally by the cell.

3. A processor cell according to Claim 1 or 2 wherein the direction-indicating means is connected to the data input of the processing means, and the control means is connected to the data output of the processing means whereby the contents of the direction-indicating means can be modified and supplied to the control means.

4. A processor cell according to any preceding claim wherein the control means is capable of causing the cell to convert data in a plurality of different ways.

5. A processor cell according to any preceding claim wherein the processing means is connected to be capable of modifying the information stored by the control means.

6. A processor cell according to any preceding claim wherein the processing means, and input/output port are capable of operating with signals representing numbers having eight binary bits.

7. A processor cell according to any preceding claim including storage means for storing data received by way of the eight input terminals.

8. A processor cell according to Claim 7 wherein the input storage means comprises a number of input registers, one corresponding to, and connected to, each input terminal, and multiplexer means for selecting any one of the input registers and applying its contents to the processing means, each input register being connected for serial loading by way of the input terminal to which it is connected and for parallel output to the multiplexer means.

9. A processor cell according to Claim 8 including means for clearing, on receipt of a further control signal, that one of the input registers which corresponds to the input terminal indicated by the direction-indicating means.

10. A processor cell according to any preceding claim wherein the processing means includes an arithmetic and logic unit, bidirectional-shifter means, and a block of storage registers, the bidirectional-shifter means and the block of storage registers being connected for loading from the arithmetic and logic unit and to apply signals simultaneously to the said unit.

11. A processor cell according to any preceding claim including terminals for the connection of a random access memory which, in operation, stores data received and transmitted by the input/output port, and data used and generated by the processing means.

12. An array of processor cells, each according to any preceding claim, the output terminal of each cell in the array being connected to one of the input terminals of at least one other cell in the array.

13. A processor cell substantially as hereinbefore described with reference to Figs. 2, 3 and 4 of the accompanying drawings.

14. An array of processor cells substantially as hereinbefore described with reference to Figs.

1 to 4 of the accompanying drawings.