JPH10304184A - Image processor and image processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor which can perform both image processings that can be performed independently by partial areas and an image processing requires a wide reference area through parallel processing at a high speed in arbitrary order. SOLUTION: Divided area data of image data are inputted to divisional input means 2 and image processes that can be performed independently by the divided areas are performed for the inputted divided area data through pipeline processing 3; and the process results of the pipeline processing 3 are integrated. Further, the image process which requires a wide reference area is performed by image processing means 5, whose processing results are integrated. Those different image processings are performed in arbitrary order to achieve fast image processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus for processing a digitized image, and more particularly to an image processing apparatus and an image processing method capable of processing an image at high speed by parallel processing. In particular, the present invention relates to an image processing apparatus and an image processing method in which a process that can be independent for each divided image data and a process that requires a wide reference area are distinguished to increase the efficiency of each process.

[0002]

2. Description of the Related Art An image processing apparatus and a DTP capable of inputting an image
In a (desktop publishing) system, a print system capable of outputting images, and the like, various image processes such as enlargement / reduction, rotation, affine transformation, filters, and color conversion are performed on large-capacity images. Since the load of these image processings is extremely large, and real-time processing is required for moving image processing, various methods have been proposed for how to perform these processings at high speed.

In general, image processing often involves repeating the same processing for many objects. As one of the techniques particularly effective for such processing, there is a method that has a plurality of processors and processing hardware, divides an image into a plurality of partial regions, and performs parallel pipeline processing.

FIG. 2 is an example of such a parallel pipeline processing system. FIG. 2 is Japanese Patent Application Laid-Open No. 5-219390.
The image data input from the scanner is divided into N regions having the same number of pixels for each row by a splitter, and each is binarized by threshold holders # 1 to #N. And compressor # 1
＃# N, integrated by the synthesizer, and output. Note that the thresholder performs a peripheral reference type binarization process that determines an output from the average value of the neighboring pixels and the pixel of interest. Therefore, the splitter removes pixels by the width of the peripheral region necessary for binarization. It is described that division is performed by overlapping.

In this configuration, since an image is divided into N regions and each is processed independently, a speedup close to N times can be expected. However, for example, a reference such as an affine transformation or a histogram equalization is used. There is a drawback that the method cannot be applied to an object that cannot be processed independently for each partial area because of a wide range. Therefore, as a method capable of performing processing including those having a wide reference range, the methods described in JP-A-3-48979 and JP-A-6-52296 have been proposed.

FIG. 3 illustrates the configuration described in Japanese Patent Application Laid-Open No. 3-48979. The image is divided from the input data bus to a plurality of existing image processing modules, input, stored in an input memory in the image processing module, processed by the arithmetic unit, and stored in an output memory. This processing result is returned to the input data bus via the output data bus, and processing for referring to all images, such as calculation of density statistical data for all images, is performed by one of the image processing modules. Parameters necessary for the next processing, such as a binarization level, are obtained and distributed to the input memory of each image processing module. Thereafter, each image processing module processes the partial image data stored in the input memory according to the parameters such as the binarization level.

In this configuration, the above-mentioned Japanese Patent Application Laid-Open No. 5-21939 is disclosed.
The configuration described in Japanese Patent Application Laid-Open No. 0-205 can be configured to enable a process requiring a large reference area, which cannot be performed by the configuration described in Japanese Patent Application Publication No. 0-086. However, since the processing requiring a large reference area is performed by one image processing module, the processing speed is slow. Further, since it is necessary to transfer the result image from the output memory side to the input memory side for each processing, a plurality of processings are continuously However, there is a disadvantage that the processing speed is reduced when performing the process.

FIG. 4 illustrates a part of the configuration described in Japanese Patent Application Laid-Open No. 6-52296. The image input from the line sensor camera is divided into partial images by a distribution circuit, digitized, processed in parallel by a pipeline processing circuit, and stored in a frame memory. The image stored in the frame memory is subjected to processing for all images by a plurality of determination control circuits and a main determination control circuit.

In this configuration, since information can be exchanged between the frame memories via the determination control circuit, a process of referring to the entire surface can also be executed. However, when each judgment control circuit needs to refer to the data in the other frame memory, control over the area becomes complicated because the frame memory is divided, and it takes time to refer to the data. It is expected that. Further, since the former pipeline processing circuit and the latter determination control circuit are separately required, there is a disadvantage that the circuit scale becomes large. Furthermore, since the order relation between the pipeline processing circuit and the determination control circuit is fixed, there is a disadvantage that a flexible configuration such as performing processing requiring a wide reference area first cannot be obtained.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the existing system, and requires image processing which can be processed independently for each partial area and partial processing for requiring a wide reference area. It is an object of the present invention to provide an image processing apparatus and an image processing method capable of processing both image processing that cannot be processed for each area at high speed and in an arbitrary order by parallel processing.

It is another object of the present invention to provide a parallel image processing apparatus which effectively uses circuits without having to have a large-scale circuit for both independent processing for each partial area and processing requiring a wide reference area. I do.

[0012]

In order to solve the above-mentioned problems, the present invention provides image storage means for storing image data,
A plurality of divided input means for respectively inputting divided area data of image data stored in an image storage means; and image processing capable of independently processing each divided area data inputted to the divided input means for each divided area Pipeline processing, a plurality of image processing pipelines, a first integrated processing unit that integrates processing results of the plurality of image processing pipelines and outputs the integrated processing results to an image storage unit, and an image stored in the image storage unit. A plurality of image processing means for reading image data and performing image processing requiring a wide reference area, and a second integrated processing means for integrating processing results of the plurality of image processing means and outputting the result to the image storage means. An image processing apparatus is provided.

An embodiment of the division input means in the image processing apparatus according to the present invention is characterized in that an image stored in the image storage means is divided into substantially the same number of pixels and input.

One embodiment of the division input means in the image processing apparatus of the present invention is to input a part of the image stored in the image storage means in accordance with the content of the processing of the image processing pipeline. It is characterized by.

Further, in the image processing apparatus of the present invention, the first
When integrating the output from the image processing pipeline according to the content of the processing of the image processing means,
The output image is extended outward by a predetermined number of pixels and stored in the image storage means. Further, the image processing means in the image processing apparatus of the present invention is characterized in that the entire input image stored in the image storage means is used as a readable area and performs processing corresponding to different areas of the output image.

Each of the image processing means in the image processing apparatus of the present invention performs processing on each area of the output image divided so that the number of target pixels is substantially equal according to the content of the processing. Features.

Further, the image processing apparatus of the present invention is realized in a multi-process or multi-thread processing environment having at least one processor, and the divided input means and the image processing pipeline have one process or one set for each set. The image processing means is processed by one process or thread.

Further, according to the image processing method of the present invention, the step of inputting the divided area data of the image data stored in the image storage means to each of the plurality of divided input means; For each data, image processing that can be independently processed for each divided region, parallel processing by a plurality of image processing pipelines,
Integrating the processing results of the plurality of image processing pipelines and outputting the result to the image storage unit, and reading the image stored in the image storage unit and performing image processing requiring a wide reference area by the plurality of image processing units And a step of integrating the processing results of the processing requiring a large reference area by the plurality of image processing means and outputting the result to the image storage means.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of an image processing apparatus and an image processing method according to the present invention will be described with reference to the drawings.

[0020]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention. In FIG. 1, an image processing device includes an image storage unit 1 for storing image data, a plurality of divided input units 2 for dividing and inputting an image stored in the image storage unit 1 for each partial area, and a divided input unit. A first integration process in which the same number of image processing pipelines 3 as the number of divided input units 2 that pipeline input from the second unit 2 and each partial image processed by the image processing pipeline are integrated and stored in the image storage unit 1 Unit 4, a plurality of image processing units 5 for processing images stored in the image storage unit 1, a second integration processing unit 6 for integrating processing results from the image processing unit 5 and storing the results in the image storage unit 1. It is composed of

The image storage unit 1 is a storage unit for storing image data, is constituted by a memory, a hard disk device, or the like, is read from the division input unit 1 or the image processing unit 5, and performs first and second integration processing. The image is input from the section. Note that input and output of images between the image storage unit 1 and the outside are performed via a scanner device or an image input I / F (not shown).

The division input section 2 divides the image data stored in the image storage section 1 into partial areas containing substantially the same number of pixels and reads out the divided image data, and reads the partial image data into each of the image processing pipelines connected thereto. Enter 3 Depending on the processing contents of the image processing pipeline, the divided input units may be divided exclusively (FIG. 5A) as shown in FIG. 5, or may overlap each other with a specific width depending on the processing parameter. It is possible to divide (FIG. 5B) so as to wrap.

The image processing pipeline 3 includes the divided input unit 2
, And sequentially processes the partial image data in a pipeline manner and outputs the partial image data to the first integrated processing unit. As shown in FIG. 7, a plurality of processing modules desired by the user are connected to each other, and when an instruction is received from the first integrated processing unit 4, the image processing pipeline 3 sequentially starts from the last module to the previous module. And the first processing module calls the divided input unit 2 connected thereto to acquire image data necessary for processing. The acquired data passes through the image processing pipeline 3 in a direction opposite to the previous instruction while being processed by each processing module, and is finally passed to the first integrated processing unit 4. This process may be performed on the entire divided partial image in a single flow, or may be performed by repeating a part of the partial image, for example, for each line.

The first integrated processing section 4 gives an instruction to the image processing pipeline 3 to start processing, receives the output processed partial image data from each image processing pipeline, and processes the processed image data. These are aligned and integrated so that the whole is created, and output to the image storage unit 1.
Further, when the processing is realized by software such as a multi-process environment or a multi-thread environment, a predetermined number of divided input units 2 are generated at the beginning of the process, and the input range is set. The image processing pipeline is configured by generating / concatenating the processed modules.

The image processing section 5 performs necessary processing while accessing the entire target image stored in the image storage section 1 in accordance with an instruction from the second integration processing section 6, and compares the result with the second integration processing. Output to the processing unit 6. Each processing range of the image processing unit 5 is set so as not to overlap on the output image output to the second integration processing unit 6. Details regarding the setting of the processing range will be described later.

The second integrated processing unit 6 gives an instruction to the image processing unit 5 to start processing, receives the output processed partial image data from each image processing unit 5, and outputs the processed image data as a whole. Are integrated so that they are created and output to the image storage unit 1. Further, when the processing is realized by software such as a multi-process environment or a multi-thread environment, a predetermined number of image processing units 5 are generated at the beginning of the process, and the output processing range is set.

Next, details of each section in the present embodiment will be described step by step. In the following description, the image is processed in the order of convolution filter, color correction, enlargement, and 45-degree rotation.
The description will be made assuming that the multi-thread environment has four processors. However, as is apparent from the configuration of the present invention, the present invention is not limited to these. Is similarly applicable. Various hardware environments such as the number of processors are not limited to the configurations described in the following embodiments.

Image data to be processed is first input from an unillustrated scanner or image input / output I / F to the image storage unit 1 and stored. First integrated processing unit 4
Obtains the size of the image to be processed from the image storage unit 1 and calculates the size of the partial area and the read start position for equally allocating the size to each divided input unit 2. At this time, the first integration processing unit 4 performs different calculations on the size of the partial area allocated to each divided input unit 2 and the read start position, depending on whether there is a process that requires peripheral pixels.

If it is not necessary to refer to peripheral pixels in the processing performed in the image processing pipeline 3, the first integrated processing unit 4
Simply creates a partial area by equally dividing the entire image into a plurality of areas. For example, when an image of 100 pixels × 100 lines is processed by four threads, the image is divided into four regions. In order to perform processing by three threads, as shown in FIG. 100 pixels x
When an image of 100 lines is equally divided into four regions, for example, as shown in Table 1 below, the target image is 10
It is divided into four regions of 0 pixels × 25 lines.

[0030]

[Table 1]-Divided area 1: (0, 0)-(99, 24)-Divided area 2: (0, 25)-(99, 49)-Divided area 3: (0, 50)-(99, 24) 74) Division area 4: (0,75) to (99,99)

When the processing performed in the image processing pipeline 3 needs to refer to peripheral pixels, the first integrated processing unit 4
Is divided so that the divided areas overlap. For example, when a 5 × 5 convolution filter is processed at the head of the image processing pipeline 3, as shown in FIG. 5B, each divided area is read by overlapping two pixels outside each divided area. It is assumed that the division input unit 2 is set to output a value of 0 pixel / line for a pixel / line smaller than 0 and a value of 99 pixels / line for a pixel / line of 100 or more. . When an image of 100 pixels × 100 lines is divided into four regions so that each divided region overlaps, for example, the image is divided into four regions as shown in Table 2 below.

[0032]

[Table 2]-Divided area 1: (-2, -2) to (101, 26)-Divided area 2: (-2, 23) to (101, 51)-Divided area 3: (-2, 48) -(101, 76)-Division area 4: (-2, 73)-(101, 101)

After calculating the size of each partial area and the read start position in this way, the first integration processing unit 4
A processing module that performs the operation of the four divided input units 2 is generated using the size of the partial area and the read position as parameters.

As shown in FIG. 6, the generated divided input unit 2 includes an input processing unit 20 for reading image data from the image storage unit 1 and a call from the first processing module of the image processing pipeline 3. And an input I / F unit 21 for outputting data read by the input processing unit 20, an address pointer for holding an address of a read position in the processing target image stored in the image storage unit 1, and a current read line position. And a line length register for holding the number of bytes of one line, and an input control unit 22 for controlling each unit. Each of these parts
The following operation is performed in response to a call from the first processing module of the image processing pipeline 3.

When a call from the head processing module of the image processing pipeline 3 occurs, the input I / F unit 21 notifies the input control unit 22 of the call, and the image data transferred from the processing module simultaneously with the call instruction. Is sent to the input control unit 22. Input control unit 22
Receives the notification from the input I / F unit 21, passes the address pointer and the contents of the line length register to the input processing unit 20, increments the line counter by 1, and if the result is greater than 0 and the image storage unit 1 Is smaller than the number of lines of the image stored in the line length register, a value corresponding to the number of bytes of one line of the image is read from the line length register and added to the address pointer. The input processing unit 20 reads data of the line length from the address of the image storage unit 1 specified by the input control unit 22 and writes the data in the area of the buffer pointer passed from the input I / F unit 21,
If extra reference pixels need to be added to the left and right, the left pixel is copied with the first pixel of the line, and the right is copied with the last pixel of the line. Thereafter, the input I / F unit 21 notifies the end processing module of the image processing pipeline 3 of the end of the reading process, and one reading process ends. The division input unit 2
Such processing is repeated in response to a call from the processing module.

After the four divided input units are generated, the first integrated processing unit 4 generates the image processing pipeline 3. First, the first integration processing unit 4 generates four convolution filter modules 30 and links each to the divided input unit 2. Next, four color correction modules 31 are generated,
Convolution filter module 3 created first for each
Link to 0. Next, four enlargement modules 32 are generated, and each is linked to the color correction module 31 created earlier. Through such processing, as shown in FIG. 7, four image processing pipelines 3 for sequentially performing a convolution filter → color correction → enlargement are generated. The filter size /
A coefficient, a color correction coefficient, an enlargement ratio, and the like are given to each module by a method such as being passed as a parameter at the time of generation.

FIG. 8 shows an internal block of the color correction module 31 as an example of these processing modules. The color correction module 31 includes an input buffer 310 for receiving an input from the preceding processing module,
An output I / F unit 311 for outputting processed data to a subsequent processing module, and a color correction processing unit 3 for performing color processing
12. When a call is made from a subsequent processing module, the output I / F unit notifies the color correction processing unit 312 of the call, and sets a pointer of a buffer for writing image data passed from the subsequent processing module at the same time as the call instruction. This is sent to the correction processing unit 312. Color correction processing unit 3
12 receives the notification from the output I / F unit 311, calls the preceding processing module with the pointer of the input buffer as an argument, receives one line of input data, and uses the coefficient stored in the coefficient register to execute the line processing. The color correction processing is performed on the data stored in the length register, the line counter is incremented by 1, and the end of the processing is notified to the output I / F unit 311. Upon receiving the processing end notification from the color correction processing unit 312, the output I / F unit 311 notifies the processing module of the subsequent stage of the processing end, and one color correction processing ends. The color correction module repeats such processing in response to a call from a processing module connected later.

When four image processing pipelines are generated, the first integrated processing unit 4 calls each image processing pipeline in parallel and performs a convolution filter → color correction → enlargement processing. FIG. 9 is an example of a block diagram illustrating a configuration of the first integration processing unit 4. The first integration processing unit 4 includes a division input unit generation unit 40 that generates the division input unit 2 described above and an image processing pipeline generation unit 41 that generates the image processing pipeline 3 described above. And an integrated control unit 42 that performs control to output the generated processing results from each image processing pipeline 3 to the image storage unit 1 while controlling the writing position. When the divided input unit 2 and the image processing pipeline 3 are generated by the processing described above, the integrated control unit 42 calls the last processing module of each image processing pipeline. At this time, each integration control unit 42 holds the start address of the area of the image storage unit 1 for writing out each divided (processed) image data in an internal address pointer, and stores this in the output buffer of the last processing module. Make a call as a pointer. The called processing module sequentially calls the processing module on the preceding stage from itself, the first module calls the divided input unit 2 to acquire data necessary for processing, and returns the processing result to the subsequent module in sequence. Is written to a predetermined address of the image storage unit 1 via the integrated control unit 42. When this process is completed once, the integrated control unit 42 increments the line counter by 1, and if it does not exceed the last line of the processing area in which it is responsible, adds the contents of the line length register to the address pointer, and again Call the last module of the image processing pipeline 3. By repeating such processing for the number of lines of each partial area, the image storage unit 1 stores all processed image data. This processing is performed by the integrated control unit 42.
And the set of the image processing pipeline 3 and the divided input unit 2 operate in one thread, and each of the four sets is processed separately in parallel. Therefore, in an environment having four or more processors, almost 1 /
The process can be executed in a time of 4.

When the above processing is completed, control is transferred to the second integration processing section 6 to perform 45-degree rotation. The second integration processing unit 6 first obtains the size of the image to be processed from the image storage unit 1, and performs processing on the output image so that the load on each image processing unit 5 becomes substantially equal based on the content of the processing. Is calculated.

When the image is rotated by 45 degrees, when the output image is divided into the same rectangle parallel to the line as shown in FIG. 10A and processed by each image processing unit 5, the pixels handled by each image processing unit There is a large difference in the numbers, and the first and fourth processes from the top end faster, whereas the second and third processes are slower, resulting in less effective parallelization. Therefore, as shown in FIG. 10B, by dividing the assigned area so that the number of output pixels assigned to each image processing unit 5 is substantially equal, it is possible to realize a speedup substantially corresponding to the number of parallel processing. Specifically, the start position and the end position of the image in each line of the output image are calculated to determine the number of pixels to be operated in each output line, and the sum of the number of pixels for each partial region is substantially equal. The area is divided into

After calculating the size and start position of each output partial area in this way, the second integration processing unit 6 sets the size and start position of each partial area and the start and end positions of each line as parameters. Four image processing units 5 that rotate by 45 degrees are generated.

As shown in FIG. 11, the generated image processing section 5 includes an input processing section 50 for reading image data from the image storage section 1 and a processing section for processing the processed data to the second integration processing section 6. It comprises an output I / F section 51 for performing output and a rotation processing section 52 for performing image rotation processing. When a call from the second integration processing unit 6 occurs, the output I / F unit 51
Notifies the rotation processing unit 52 of this fact, and sends a pointer of a buffer for writing the image data passed from the second integration processing unit 6 to the rotation processing unit 52 at the same time as the call instruction. The rotation processing unit 52 obtains the start pixel position and the end pixel position from the start / end pixel position table for the processing target line stored in the line counter, and sequentially stores the coefficients stored in the coefficient register from the start position to the end position. Is used to find a corresponding pixel position in the original image, and the value of that pixel is input to the input processing unit 5.
The data is read out from the image storage unit 1 via 0 and written into the output buffer. When the processing reaches the end pixel position, the rotation processing unit 6 increments the value of the line counter by 1 and notifies the output I / F unit 51 of the end of the processing. Output I
Upon receiving the processing end notification from the rotation processing unit 52, the / F unit 51 notifies the second integration processing unit 6 of the processing end, and
The rotation processing for one line of the output image ends. The image processing unit 5 repeats such processing in response to a call from the second integration processing unit 6.

When the four image processing units 5 are generated, the second integrated processing unit 6 calls each image processing unit 5 in parallel and performs a 45-degree rotation process. FIG. 12 is an example of a block diagram illustrating a configuration of the second integration processing unit 6. The second integration processing unit 6 includes an image processing unit generation unit 60 for generating the image processing unit 5 described above and a writing position of the generated processing result from each image processing unit 5 in the image storage unit 1. And an integrated control unit 61 for performing control for outputting while controlling. When the image processing unit 5 is generated by the processing described above, the integrated control unit 61 calls each image processing unit. At this time, each integrated control unit 61 holds the start address of the area of the image storage unit 1 for writing out the processed data from each image processing unit in an internal address pointer, and stores this in the output buffer of the image processing unit 5. Call as a pointer to The called image processing unit 5 calculates the pixels between the start / end pixel positions as described above.
The value of the corresponding point on the original image is read out from the image storage unit 1 and output, and when this is completed, the processing result of the line is stored in the image storage unit 1 via the second integration processing unit 6. Is written in the area for When this process is completed once, the integrated control unit 61 increments the line counter by 1, and if it does not exceed the last line of the processing area in which it is responsible, adds the contents of the line length register to the address pointer, and again The image processing unit 5 is called.
By repeating such processing for the number of lines in each partial area, the image processing unit 1 stores the final processed all image data. In this processing, the set of the integrated control unit 61 and the image processing unit 5 operates in one thread, and the four sets are separately processed in parallel, and the number of pixels to be processed by each set is substantially equal. Almost 1/4 in an environment with four or more processors because the number of lines is assigned
The process can be executed in a time of.

In this embodiment, the processing is performed in the order of convolution filter → color correction → enlargement → rotation by 45 degrees. However, as is apparent from the configuration, the processing is as wide as 45 degrees rotation → convolution filter → color correction → enlargement. Even if the processing that requires the reference area is the first processing order, the processing that requires a wide reference area such as a convolution filter → rotation by 45 degrees → color correction → enlargement, or the processing that requires a wide reference area Even if there is a plurality, high-speed processing by parallel processing is possible in the same manner.

If the processing requiring a wide reference area such as 45-degree rotation → convolution filter → color correction → enlargement is the first processing order, the configuration is changed as shown in FIG. If the output can be directly input to the image processing pipeline 3, the data read from the image storage unit 1 is subjected to 45-degree rotation processing by the image processing unit 5, and then the processed data is input to the image processing pipeline 3. For each data, a convolution filter → color correction → enlargement processing can be executed. According to this configuration, it is not necessary to temporarily store all image data in the image storage unit 1, and it is possible to save a memory area.

Further, in the first integrated processing unit 4 and the second integrated processing unit 6 of this embodiment, the image processing pipeline 3
Alternatively, the output of the image processing unit 5 is simply integrated and the image storage unit 1
However, as shown in FIG. 14, it is also possible to provide a region of a specific width around the output image and fill it with the same value as the outermost pixel value, according to the next processing. is there. With this configuration, when a reference outside the input image occurs such as a 45-degree rotation in which the processing in the image processing unit 5 performs a 9-point quadratic interpolation, the first integration processing unit 4 accordingly By writing the output image by providing the peripheral area of, the image processing unit 5 does not need to determine whether or not the reference pixel position is outside the image, and the speed can be increased.

Further, the present embodiment has been described as being realized in a multi-thread environment having a plurality of processors. However, realization in a multi-process environment, a DSP (Digital Signal Processor) and an FPGA (Field
It may be realized by programmable hardware such as a programmable gate array, or may be configured by fixed hardware such as a gate array although the circuit scale increases.

In this embodiment, when there are four processors, the set of the divided input unit 1, the image processing pipeline 3, and the image processing unit 5 are executed by the same four threads. When not all processors can be assigned only to an image as in the expansion processing of the description language), the configuration may be such that the processing is executed by four or less threads, or the number of threads is varied according to the load of other processing. It is possible.

In this embodiment, the processing is performed on a line basis. However, the present invention is not limited to this. The same applies to various processing units such as a pixel unit, a plurality of line units, and a block unit. Can be implemented.

[0050]

As described above, the image processing apparatus according to the present invention can perform processing independently for each partial region of a processed image, such as a convolution filter, color correction, and enlargement, and a wide reference such as a 45-degree rotation. High-speed processing can be performed in an arbitrary order for both of which cannot be independently processed for each partial area because of the need for areas. In addition, multi-process or multi-thread environments with multiple processors, DS
By realizing the configuration of the present invention with programmable hardware such as P (Digital Signal Processor) and FPGA (Field Programmable Gate Array), independent processing for each partial area of the processed image and wide reference It is possible to provide a parallel pipeline type image processing device that effectively uses a circuit without having a large-scale circuit for processing that requires an area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an existing image processing apparatus.

FIG. 3 is a block diagram illustrating another configuration of an existing image processing apparatus.

FIG. 4 is a block diagram illustrating another configuration of an existing image processing apparatus.

FIG. 5 is a diagram illustrating division of an image in a division input unit 2.

FIG. 6 is a block diagram showing a divided input unit 2.

FIG. 7 is a block diagram showing an image processing pipeline 3.

FIG. 8 is a block diagram showing a color correction module 31.

FIG. 9 is a block diagram showing a first integration processing unit 4;

FIG. 10 is a diagram illustrating setting of a divided area in image data rotation processing.

FIG. 11 is a block diagram illustrating an image processing unit 5;

FIG. 12 is a block diagram showing a second integration processing unit 6;

FIG. 13 is a block diagram showing another configuration according to the embodiment of the present invention.

FIG. 14 is a diagram illustrating an output method in the first integration processing unit 4 or the second integration processing unit 6.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 image storage unit 2 divided input unit 3 image processing pipeline 4 first integrated processing unit 5 image processing unit 6 second integrated processing unit 20 input processing unit 21 input I / F unit 22 input control unit 30 convolution filter module 31 Color correction module 32 Enlargement module 40 Divided input unit generation unit 41 Image processing pipeline generation unit 42 Integrated control unit 50 Input processing unit 51 Output I / F unit 52 Rotation processing unit 60 Image processing unit generation unit 61 Integrated control unit 310 Input buffer 311 output I / F section 312 color correction processing section

Claims (8)

[Claims] An image storage unit for storing image data; a plurality of divided input units for respectively inputting divided region data of the image data stored in the image storage unit; and a divided region input to the divided input unit A plurality of image processing pipelines that execute image processing that can be independently processed for each divided region by pipeline processing for each data; and the image storage unit that integrates processing results of the plurality of image processing pipelines. A plurality of image processing means for reading out an image stored in the image storage means and performing image processing requiring a wide reference area; and integrating processing results of the plurality of image processing means. And a second integrated processing means for outputting the image data to the image storage means. 2. The image processing apparatus according to claim 1, wherein the division input unit divides the image stored in the image storage unit into regions each having substantially the same number of pixels and inputs the divided regions. 3. The image processing apparatus according to claim 1, wherein the division input unit inputs the images stored in the image storage unit in a partially overlapping manner in accordance with the contents of the processing of the image processing pipeline. An image processing apparatus according to claim 1. 4. The image processing apparatus according to claim 1, wherein the first integration processing unit is configured to integrate the output from the image processing pipeline with a predetermined number of pixels outward when integrating the output from the image processing pipeline in accordance with the content of the processing of the image processing unit. The image processing apparatus according to claim 1, wherein the image processing apparatus expands only the image data and stores it in the image storage unit. 5. The image processing unit sets the entirety of the input image stored in the image storage unit as a readable area,
The image processing apparatus according to claim 1, wherein processing corresponding to different regions of the output image is performed. 6. The image processing device according to claim 1, wherein each of the image processing units performs a process on each area of the output image divided so that the number of target pixels is substantially equal according to the content of the process. 6. The image processing device according to 5. 7. A multi-process or multi-thread processing environment having at least one processor, wherein the divided input means and the image processing pipeline are processed by one process or thread for each set, and 7. The image processing apparatus according to claim 1, wherein each of the units is processed by one process or thread. 8. A step of inputting the divided area data of the image data stored in the image storage means to a plurality of divided input means, respectively, for each of the plurality of divided area data inputted to the divided input means, Parallel processing of image processing that can be independently processed by a plurality of image processing pipelines; integrating the processing results of the plurality of image processing pipelines and outputting the integrated processing results to the image storage unit; Reading an image stored in the image storage unit and performing image processing requiring a wide reference area by a plurality of image processing means; and integrating the processing results of the processing requiring a wide reference area by the plurality of image processing means into the image storage Outputting to the means.