KR100971148B1 - Parallel structure image processing apparatus and method for image matching with adjusting intensities - Google Patents

Abstract

The present invention relates to an image processing apparatus and method having a parallel structure for image registration through brightness control.

According to an aspect of the present invention for achieving the above object, in the image processing apparatus of a parallel structure performing a matching operation between one or more images, an image acquisition unit for receiving the one or more images to obtain image data And an image buffer for temporarily storing the obtained image data. A normalization processing unit for normalizing the acquired-buffered image data received from the image buffer, a division processing unit for dividing the normalized image data to a size of a window used in a system, and a window in which the normalized-divided image data is temporarily stored. A preprocessing block comprising a buffer; And a data cost calculator configured to calculate a data cost by applying a normalized cross-correlation to the normalized-split-buffered image data received from the window buffer. A hierarchical iterative operation unit performing a hierarchical iterative operation of the reliability transfer method and outputting a message value at the end of the iterative operation to each node, and collecting the message values for each node, so that the accumulated value is minimized. An image matching block including a state estimator for estimating a state and outputting a displacement value of a corresponding point is provided.

According to the present invention, it is possible to implement a robust real-time image registration system even in an environment in which a bias phenomenon due to an illumination difference exists due to memory saving and computation time reduction due to a decrease in the number of repetitive operations.

Brightness control, image matching, reliability transfer, parallel structure, normal cross correlation

Description

Parallel structure image processing apparatus and method for image matching with adjusting intensities

The present invention relates to an image processing apparatus and method having a parallel structure for image registration through brightness control. In detail, the present invention provides an image processing apparatus having a parallel structure that performs reliable image matching at a high speed by adjusting an intensity of a corresponding part when an illumination difference exists in a plurality of images in time or space. It is about a method.

Conventional methods for searching for and estimating a matching portion of a specific pixel or image region for a plurality of images can be broadly classified into two types. Local matching technique that finds a match point using only limited information based on pixel or pixel window, and global matching technique that collects the information of the whole image and estimates the match point will be.

Global matching techniques generally suffer from high computational complexity and high system complexity, but have much lower error rates than local matching techniques and provide stable results against occlusion. Reliability propagation (BP), one of the global matching techniques, is one of Bayesian estimation techniques in graph structures based on the Hidden Markov Model (HMM). It is a global matching technique characterized by a phosphorus operation structure. The reliability transfer method estimates a hidden state having a minimum probability energy by repeatedly performing probability message exchange between neighboring nodes on a graph composed of branches connecting nodes and neighboring nodes.

Global matching based on reliability transfer shows better performance than other matching, but it is difficult to process in real time due to very large memory and computational complexity. In order to solve this problem, an improved reliability transfer method using a layering method and a distance conversion method has been proposed and based on this, a real-time system using a parallel graphics processing unit (GPU) has been implemented. The processing performance was limited due to the limited parallelism of the operation. Fast Belief Propagation (FBP), a more advanced iterative computation method, has recently been developed to solve the problem of high memory bandwidth and memory capacity by improving the iterative computation structure of the existing reliability propagation technique. The Scale Integration (Scale Integration) structure allows for a higher level of parallelism. The image matching system based on the fast reliability transmission structure and method shows superior image processing performance while using a significantly reduced memory and a slower clock frequency than the conventional reliability delivery systems.

Conventional image transfer systems based on reliability transfer show good results under ideal lighting conditions in the room, but due to external factors such as reflected light, shadows in hidden areas, uneven camera settings, and relative positions of lights and cameras, Large error occurs when the bias of pixel brightness occurs at. This is because the existing data cost expressing the difference in brightness of pixels has a similar brightness distribution form, but the similarity of the portion where the brightness of a specific portion is biased cannot be accurately determined.

Therefore, in order to realize a reliability matching-based image matching system with robust performance in various lighting conditions, a method of removing the bias phenomenon by normalizing the brightness of the part where the illumination difference is caused by the bias phenomenon is required. As a result, many methods based on reliability transfer have obtained good results by applying the normalized cross-correlation (NCC) to the data cost.

Correlation based on the pixel window is a method of measuring the similarity of an image. The correlation coefficient between an image and feature vectors of a pixel window in a comparison image is determined. Expressed as the squared value. The method using the correlation coefficient is more reliable than the method of using the absolute value of the brightness difference between single pixels by comparing a plurality of pixels, but due to the difference in illumination of part or all of a similar pattern of image brightness It does not work well when there is a bias. The normal cross correlation coefficient can minimize the influence of biasing on the matching process by normalizing a feature vector having a mean of 0 and extracting only the direction vector.

However, a system based on a normal cross correlation coefficient has a high computational complexity of O (n ⁴ ) and requires a lot of multiplication, division, and square root operations and thus is not suitable for a parallel processing system based on VLSI.

Therefore, in order to implement a real-time image matching system requiring high reliability in various environments, a brightness control method having a structure suitable for parallel processing is required.

According to an aspect of the present invention for achieving the above object, in the image processing apparatus having a parallel structure for performing a matching operation between one or more images, the image acquisition unit and the acquisition to obtain the image data by receiving the one or more images; An image acquisition block including an image buffer for temporarily storing one image data; A normalization processing unit for normalizing the acquired-buffered image data received from the image buffer, a division processing unit for dividing the normalized image data to a size of a window used in a system, and a window in which the normalized-divided image data is temporarily stored. A preprocessing block comprising a buffer; And a data cost calculator configured to calculate a data cost by applying a normal cross-correlation coefficient to the normalized-split-buffered image data received from the window buffer, and perform the hierarchical iterative operation of the fast reliability transfer method by receiving the data cost. A hierarchical iterative operation unit which outputs the message value at the end of the iteration operation to each node and the message value are collected for each node, and the state in which the accumulated value is minimized is estimated as the hidden state of the corresponding node and the displacement value of the corresponding point is output. An image matching block including a state estimator is provided.

According to another aspect of the present invention for achieving the above object, in a parallel image processing method for performing a matching operation between one or more images, the image acquisition unit obtains the image data from the one or more images received from a plurality of cameras Obtaining an image; An acquired image storing step of temporarily storing the obtained image data by an image buffer; A normalization step of normalizing, by the normalization processing unit, the acquired-buffered image data received from the image buffer; A division step of dividing the normalized image data by the division processing unit according to a size of a window used in a system; A divided image storing step of temporarily storing the normalized-divided image data by a window buffer; A data cost calculation step of calculating a data cost by a data cost calculator applying a normal cross correlation coefficient to the normalized-split-buffered image data received from the window buffer; A hierarchical repetition operation step of receiving a data cost by the hierarchical repetition operation unit and performing a hierarchical repetition operation of a fast reliability transfer method to output a message value at the end of the repetition operation to each node; And a state estimating step of collecting, by the state estimator, the message value for each node, estimating a state in which the accumulated value is minimum as a hidden state of the corresponding node, and outputting a displacement value of the corresponding point. To provide.

According to the present invention, far-field information is quickly converged by using a hierarchical operation structure of a fast reliability transfer method in an image matching system to which a normal cross correlation coefficient is applied. As a result, the number of repetitive operations required is significantly reduced compared to the existing system based on reliability transfer, which saves memory and reduces computation time.

In addition, since the high-speed reliability transfer method is easy to parallelize using VLSI, it is possible to implement a robust real-time image matching system that shows stable performance even in the presence of a bias due to a light difference.

Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to intention or custom of a user or an operator. Therefore, the definition should be made based on the contents throughout the specification.

1 is a block diagram of an entire image processing system 100. The image processing system 100 includes a series connection structure of an image acquisition block 101, a preprocessing block 102, and an image registration block 103. The image acquisition block 101 receives a plurality of images 105, sequentially processes the image acquisition unit 110 and the image buffer 120 as lower components, thereby obtaining and buffering the image data 125. Is output to the preprocessing block 102. The preprocessing block 102 receives the acquisition-buffered image data 125 and performs processing in the normalization processing unit 130, the division processing unit 140, and the window buffer 150, which are sub-components, in order, and normalizes them. The divided-buffered image data 155 is output to the image registration block 103. The image matching block 103 receives the normalized-divided-buffered image data 155 and outputs the sub-component data cost calculator 160, the hierarchical iterative operator 170, and the state estimator 180. The processing is carried out in sequence to output the displacement value 185 of the corresponding point.

The image acquisition block 101 has a serial connection structure between the image acquisition unit 110 and the image buffer 120.

The image acquirer 110 extracts the acquired image data 115 in the form of streaming data or video file from the plurality of images 105 by a plurality of cameras, and transmits the obtained image data 115 to the image buffer 120. A frame grabber or a video decoder corresponds to this. In the case of an image matching system using two or more cameras, a portion for synchronizing the camera trigger and the image transmission is necessary in addition to the image acquisition unit 110. The plurality of images 105 to be input are digital images by multiple cameras having the same resolution, and the obtained original image and the comparison image are the same size.

The image buffer 120 sequentially stores the acquired image data 115 which is continuously transmitted from the image acquisition unit, and outputs the image data 115 as the acquisition-buffered image data 125 according to a user's request. ring buffer) memory, which acts as an intermediate storage for images essential for pixel window-based image processing.

The preprocessing block 102 has a serial connection structure of the normalization processing unit 130, the division processing unit 140, and the window buffer 150.

2 is a block diagram of the normalization processor 130. The normalization processor 130 includes a deviation calculation module 240, an L1 norm calculation module 250, and a divider 260.

The deviation calculation module 240 includes a scan line buffer 210, an average calculation module 220, and a subtractor 230. The scan line buffer 210 receives the acquired-buffered image data 125 from the image acquisition block 101, obtains and temporarily stores the scanned image data value 215 coming in units of scan lines of the image, and calculates the average thereof. Output to module 220 and subtractor 230. The average calculation module 220 receives the scan image data value 215 of the pixel window from the scan line buffer 210, obtains the average 225, and outputs the average 225 to the subtractor 230. The subtractor 230 subtracts the average 225 of the scan image data values 215 received from the average calculation module 220 from the scan image data values 215 received from the scan line buffer 210, thereby subtracting the average of the pixel values. The deviation 235 of the mean is output to the L1 norm calculation module 250 and the divider 260. This task makes the mean of the coordinates of the feature vector of the image data used to calculate the deviation 235, the normal cross correlation coefficient, to zero. In this case, the number of pixels in the pixel window can be specified to be an exponent of 2 so that the calculation of the average can be made through simple bit shift. In this case, the average calculation module 220 may accumulate the accumulator 222 and the shift register. , 224). The accumulator 222 temporarily adds all the scan image data values 215 received from the scan line buffer 210 and temporarily stores them. Since the number of pixels is an exponent of 2, the shift register 224 stores the value received from the accumulator 222. Divide operations are performed just by moving bits, which increases the computation speed.

The L1 norm calculation module 250 consists of an absolute value calculator 252 and an adder 254. The L1 norm is a method of indicating the size of a vector, also called a city block distance, and is expressed as a sum of absolute difference (SAD) of each coordinate value of the vector. The absolute value calculator 252 receives a feature vector having a mean of 0, that is, a deviation 235 of the pixel value and the mean from the deviation calculating module 240, and adds the absolute value 253 from which the sign is removed to the adder 254. Output The adder 254 outputs the L1 norm value 255 of the feature vector, which is the sum of the absolute values 253, to the divider 260. The introduction of the L1 norm, rather than the Euclidean norm, can significantly reduce computation time and the number of logic circuits.

The divider 260 divides the feature vector whose mean is 0, that is, the deviation 235 of the pixel value and the mean by the L1 norm value 255 of the feature vector. Through this process, the feature vector is converted into a direction vector to become normalized image data 135 output to the division processor 140.

The division processor 140 divides the normalized image data 135, which is the pixel data passed through the normalization processor 140, according to the size of the pixel window used in the system, and outputs the normalized image data 135 to the window buffer 150.

The window buffer 150 gradually stores the normalized-segmented image data 145, which is the divided pixel data received from the division processor 140, and outputs it to the image matching block 103. FIG. The window buffer 150 may have a parallel structure for data cost synchronization when the image matching block 103 has a parallel structure.

3 is a block diagram of a window buffer 150 in a parallel structure. The window buffer 150 has a structure in which a total of N buffers 320 are connected in parallel, and each buffer 320 has a structure in which S window memories 310 are connected in series, such as the total number of states of a reliability delivery system. 310 stores the entire pixel within a single pixel window. That is, the N buffers 320 having a depth S exist in the window buffer 150 in a parallel structure. Each of the window buffers 150 operates in parallel with respect to the same state, and the update of the window memory 310 is made gradually according to the change of state.

The structure of the preprocessing block 102 prevents excessive logic circuit waste that can be caused by the introduction of a regular cross correlation coefficient in a parallel computing system implemented with a VLSI structure, and makes pixel window matching easier.

The image matching block 103 has a series connection structure of the data cost calculator 160, the hierarchical repetition calculator 170, and the state estimator 180.

4 is a block diagram of the data cost calculator 160. The data cost calculator 160 includes a hierarchical data cost calculator 420 and a data cost memory 430 that receive outputs from the calculator modules 410 in parallel in a structure in which the operator modules 410 are connected in parallel. ) Is structured in series. The data cost calculator 160 corresponds to one operation group on a graph having M hierarchical levels, and a total of N = 2 ^M-1 operator modules 410 are connected in parallel.

The operator module 410 has a series connection structure of an absolute difference calculator 412, an accumulator 414, and a moving register 416. The absolute difference calculator 412 receives the normalized-split-buffered image data 155 and calculates an absolute value, that is, an absolute difference between all pixel values of the original window and the comparison window. The accumulator 414 adds the absolute difference and temporarily stores it. The shift register 416 outputs, to the hierarchical data cost calculator 420, a value obtained by converting the input received from the accumulator 414 into 1/2 in bit shift.

The hierarchical data cost calculator 420 receives the outputs from the total N operator modules 410 in parallel and outputs the data cost values obtained through the hierarchical operation of the fast reliability transfer method to the data cost memory 430. .

The data cost memory 430 stores the data cost value received from the hierarchical data cost calculator 420, and outputs the data cost 165 to the hierarchical iteration operation unit 170.

5 is a block diagram of the hierarchical iteration operation unit 170. The hierarchical iteration operation unit 170 includes M operation groups 510 connected in parallel and whether to determine whether to repeat the iteration operation 520. Each operation group 510 is composed of one local buffer (512), one parallel processing unit (PE, 514), and one layer buffer (516), and a two-dimensional graph. It performs the message calculation and the repetitive message update operation to which hierarchical repetition operation of fast reliability transfer method is applied to one node on the network.

The operation group 510 uses the data cost 165, the message 515 in the previous iteration step, and the smoothness cost function between the nodes to assign the message value 517 to the nodes of the graph of the same size as the image. Output The layer buffer 516 receives the message value 517 and temporarily stores the message value 517, and outputs the message to the determination unit 520. The repetition operation end determination unit 520 determines whether to terminate the hierarchical repetition operation whenever the layer buffer 516 is updated. If not, the message 515 in the previous repetition step is calculated. The message value 175 at the end of the repetitive operation is output to the state estimator 180 when it is finished.

6 is an embodiment of a hierarchical graph structure of a hierarchical reliability transfer scheme. In the fast reliability transfer technique, hierarchical reliability transfer (Hierarchical BP) method is used to obtain converged results with a fixed number of iterative operations. The hierarchical reliability transfer technique undersamples a graph of a given size to produce a multilevel parent graph with fewer nodes, and the orientation of the child graph in the parent graph for the graph pyramid similar to the image pyramid created here. Coarse-to-fine iterative operation. In FIG. 6, since the upper graph k + 1 is a graph obtained by under-sampling the graph below the first stage (k), the approximate information of the graph in the lower stage may be represented by using 1/4 times fewer nodes.

7 is one embodiment of fast reliability delivery in the graph of FIG. In the fast reliability transfer method, iterative operations on a graph are sequentially processed in parallel along the scanline direction of an image using a local buffer and a layer buffer structure. When all the iterations of the upper graph are finished, the message value of each upper node calculated based on this initializes the message of the node on the corresponding lower graph. This is the process of applying the information obtained through the iterative operation on the upper graph, and it is possible to collect the information of the remote nodes at high speed to reduce the number of iterations.

According to the above characteristic of the hierarchical graph structure, in the hierarchical graph structure having a total of M levels, one node of the graph of the highest level includes information of 2 ^M-1 × 2 ^M-1 lowest nodes. Assuming the width of the image is C and C is a multiple of 2 ^M-1 , the maximum number of parallel processors required is C and the minimum number of parallel processors required is C / 2 ^M-1 . Therefore, a parallel processor may be divided into C / 2 ^M-1 groups of operations consisting of N = 2 ^M-1 processors. The parallel window buffer 150 is shown in FIG. 3, and the parallel data cost calculator 160 is shown in FIG. 4.

The state estimator 180 collects the message value 175 at the end of the iteration operation received from the hierarchical iteration operator 170 for each node, and displays a hidden state of the node in which the accumulated value is minimum. It estimates as and outputs the displacement value 185 of the corresponding point.

The estimated state of the node is a displacement value between pixels of the original image of the corresponding coordinates and pixels and coordinates of the corresponding comparison image, which are output in a two-dimensional array having the same size as the image. The output displacement value 185 of the corresponding point corresponds to each discrete coordinate of the array, and is a two-dimensional array structure of the same size as the input reference image, and the pixel at the same coordinate in the reference image and its comparison The difference in image coordinates between corresponding pixels in an image.

Next, the image processing method 800 by the image processing system 100 described above will be described with reference to the flowchart shown in FIG. 8.

The image acquisition unit 110 of the image acquisition block 101 receiving the plurality of images 105 from the plurality of cameras acquires the image data 115 from the plurality of images 105 (image acquisition step, S1). This is temporarily stored in the image buffer 120 of the image acquisition block 101 (acquisition image storage step, S2). At this time, the obtained image data 115 includes streaming data or a video file type.

In the deviation calculation module 240 of the normalization processor 130 of the preprocessing block 102, the scan image buffer value 215 is received from the scan line buffer 210, and the average calculation module 220 obtains an average 225 and subtracts the subtractor. The 230 outputs the deviation 235 of the scan image data value 215 and its average 225. In the L1 norm calculation module 250, the absolute value calculator 252 calculates the absolute value 253 of the deviation 235 and the adder 254 adds it to calculate the L1 norm value 255, and the divider 260 The deviation 235 is divided by the L1 norm value 255 to obtain normalized image data 135 (normalization step, S3). The division processor 140 divides the normalized image data 135 in accordance with the size of the pixel window used in the system (dividing step S4), and the window buffer 150 temporarily stores the normalized-divided image data 145. Save (Split image storage step, S5). The window buffer 150 may be a parallel structure of N buffers 320 having a depth S.

The data cost calculator 160 of the image matching block 103 calculates the data cost 165 (data cost calculation step S6), at which time the operator module 410 of the data cost calculator 160 performs a window buffer. There may be the same number of parallel structures as 150.

9 is a flowchart of the hierarchical iterative operation step S7. The hierarchical iterative operation step S7 is a step subsequent to the data cost calculation step S6, and receives and processes the data cost 165 from the data cost calculation step S6. The operation group 510 uses the data cost 165, the message 515 in the previous iteration step, and the smoothness cost function between the nodes to assign the message value 517 to the nodes of the graph of the same size as the image. Output (message calculation step, S7-1). The layer buffer 516 receives the message value 517 and temporarily stores the message value 517, and outputs the result to the determination unit 520 whether the iterative operation ends (temporary storage step S7-2). The repetition operation end determination unit 520 determines whether to terminate the hierarchical repetition operation whenever the layer buffer 516 is updated. If not, the message 515 in the previous repetition step is calculated. In step 510, when it is terminated, the message value 175 at the end of the repetitive operation is output to the state estimator 180 (step of determining whether the repetitive operation ends, S7-3).

The state estimator 180 collects the message values of the output nodes for each node and estimates the state in which the accumulated value becomes the minimum as a hidden state of the corresponding node (state estimation step S8). Outputs a displacement value of 185.

Although the embodiments have been described for the understanding of the present invention as described above, it will be understood by those skilled in the art, the present invention is not limited to the specific embodiments described herein, but variously without departing from the scope of the present invention. May be modified, changed and replaced. Therefore, it is intended that the present invention cover all modifications and variations that fall within the true spirit and scope of the present invention.

1 is a block diagram of an entire image processing system 100.

2 is a block diagram of the normalization processor 130.

3 is a block diagram of the window buffer 150.

4 is a block diagram of the data cost calculator 160.

5 is a block diagram of the hierarchical iteration operation unit 170.

6 is an embodiment of a hierarchical graph structure of a hierarchical reliability transfer scheme.

7 is one embodiment of fast reliability delivery in the graph of FIG.

8 is a flowchart of an image processing method 600 by the system 100.

9 is a flowchart of the hierarchical iterative operation step S7.

Claims (29)

An image processing apparatus having a parallel structure that performs a matching operation between one or more images, An image acquisition block including an image acquisition unit configured to receive the at least one image and to obtain image data, and an image buffer to temporarily store the obtained image data; A normalization processing unit for normalizing the acquired-buffered image data received from the image buffer, a division processing unit for dividing the normalized image data to a size of a window used in a system, and a window in which the normalized-divided image data is temporarily stored. A preprocessing block comprising a buffer; And A data cost calculator configured to calculate a data cost by applying a normalized cross-correlation to normalized-segmented-buffered image data received from the window buffer; A hierarchical iterative operation unit performing a hierarchical iterative operation of the transfer method and outputting a message value at the end of the iteration operation to each node, and collecting the message values for each node, and a state in which the accumulated value is minimized is hidden. an image matching block including a state estimator for estimating a hidden state and outputting a displacement value of a corresponding point; Image processing apparatus having a parallel structure. The method of claim 1, The image data obtained by the image acquisition unit is one of streaming data or a video file type. Parallel image processing device. The method of claim 1, The image acquisition unit includes any one of a frame grabber or a video decoder. Parallel image processing device. The method of claim 3, wherein The image acquisition unit further includes a synchronization unit for camera trigger and image transmission. Parallel image processing device. The method of claim 1, The image buffer has a ring buffer structure Parallel image processing device. The method of claim 1, wherein the normalization processing unit A deviation calculation module which subtracts an average of the scan image data values from the scan image data values for the image data and obtains the deviation as a feature vector of the image data; An L1 norm calculation module for calculating an L1 norm of the feature vector; And A divider dividing the feature vector by the L1 norm; Image processing apparatus of a parallel structure comprising a. The method of claim 6, wherein the deviation calculation module A scan line buffer configured to temporarily store a value of the scan image data received in units of scan lines; An average calculation module for calculating an average of the scanned image data values; And A subtractor for subtracting the average from the scan image data values; Image processing apparatus of a parallel structure comprising a. The method of claim 7, wherein The size of the image data is an index of two, The average calculation module An accumulator for temporarily storing the scanned image data value; And A shift register for bit-shifting the output of the accumulator to obtain an average; Image processing apparatus of a parallel structure comprising a. The method of claim 6, wherein the L1 norm calculation module An absolute value calculator for calculating an absolute value of the deviation received from the deviation calculation module; And An adder for adding the absolute value; Image processing apparatus of a parallel structure comprising a. The method of claim 1, The window buffer is a parallel window buffer, The data cost calculator includes the same number of parallel calculator modules as the parallel window buffer. Parallel image processing device. The method of claim 10, wherein the parallel window buffer Contains one or more buffers connected in parallel, The buffer includes one or more window memories connected in series. Parallel image processing device. The method of claim 1, wherein the hierarchical iteration operation unit implements a fast reliability transfer method. At least one operation group connected in parallel and including a determination whether the end of the repeat operation Parallel image processing device. The method of claim 12, wherein each operation group, Including local buffers, parallel units of operations, and layer buffers Parallel image processing device. The method of claim 1, The image data may be in the form of window pixels. Parallel image processing device. The method according to any one of claims 1 to 14, Including the device Image registration system. In the parallel image processing method for performing a matching operation between one or more images, An image acquiring step of acquiring image data from the one or more images received by the image acquiring unit; An acquired image storing step of temporarily storing the obtained image data by an image buffer; A normalization step of normalizing, by the normalization processing unit, the acquired-buffered image data received from the image buffer; A division step of dividing the normalized image data by the division processing unit according to a size of a window used in a system; A divided image storing step of temporarily storing the normalized-divided image data by a window buffer; A data cost calculation step of calculating a data cost by a data cost calculator applying a normal cross correlation coefficient to the normalized-split-buffered image data received from the window buffer; A hierarchical repetition operation step of receiving a data cost by the hierarchical repetition operation unit and performing a hierarchical repetition operation of a fast reliability transfer method to output a message value at the end of the repetition operation to each node; And A state estimating step of a state estimator collecting the message values for each node, estimating a state in which the accumulated value is minimum as a hidden state of the corresponding node, and outputting a displacement value of a corresponding point; Including, the image processing method of a parallel structure. The method of claim 16, The image data obtained by the image acquisition unit is one of streaming data or a video file type. Image processing method of parallel structure. The method of claim 16, The image acquisition unit includes any one of a frame grabber or a video decoder. Image processing method of parallel structure. The method of claim 18, The image acquisition unit further includes a synchronization unit for camera trigger and image transmission. Image processing method of parallel structure. The method of claim 16, The image buffer has a ring buffer structure Image processing method of parallel structure. 17. The method of claim 16, wherein said normalizing step A deviation calculation step of subtracting an average of the scan image data values from the scan image data values for the image data and obtaining the deviation as a feature vector of the image data; An L1 norm calculating step of calculating an L1 norm of the feature vector; And Dividing the feature vector by the L1 norm; Including, the image processing method of a parallel structure. The method of claim 21, wherein the step of calculating the deviation A scan line buffering step of temporarily storing a value of the scan image data in which scan line buffers are input in units of scan lines; An average calculating step of calculating, by the average calculating module, the average of the scanned image data values; And A subtractor subtracting the average from the scan image data values; Including, the image processing method of a parallel structure. 23. The method of claim 22, The size of the image data is an index of two, The average calculation step An accumulator temporarily storing the scanned image data value; And A shift register bit shifting the output of the accumulator to obtain an average; Including, the image processing method of a parallel structure. 22. The method of claim 21 wherein the L1 norm calculation step is An absolute value calculating step of obtaining, by an absolute value calculator, an absolute value of the deviation received from the deviation calculating module; And An adding step wherein an adder adds the absolute value; Including, the image processing method of a parallel structure. The method of claim 16, The window buffer is a parallel window buffer, The data cost calculator includes the same number of parallel calculator modules as the parallel window buffer. Image processing method of parallel structure. 27. The system of claim 25, wherein the parallel window buffer is Contains one or more buffers connected in parallel, The buffer includes one or more window memories connected in series. Image processing method of parallel structure. The method of claim 16, The hierarchical iterative operation step uses a fast reliability transfer method, A message calculation step in which a calculation group outputs a message value to a node of a graph having the same size as an image using the data cost, the message delivered in a previous repetition step, and a flat cost function between nodes, A buffering step of temporarily storing the output message value in a layer buffer; An iterative operation end determination step of determining whether or not the iterative operation ends when the layer buffer is updated; Including, the image processing method of a parallel structure. 28. The method of claim 27, wherein said message calculating step The operation group may be sequentially processed in parallel along the scan line direction of the image by using a structure including a local buffer, a parallel operation unit, and a layer buffer. Image processing method of parallel structure. The method according to any one of claims 16 to 28, The image data is a window pixel Image processing method of parallel structure.

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