JP2014157411A - Data processing device, control method thereof, and data processing program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve parallel processing of data without requiring complicated arithmetic processing in advance for allocating divided areas and memory addresses.SOLUTION: A data processing device includes: a first processing unit 203 which performs processing by starting to read data from a first position (for example, a head position); and a second processing unit 205 which performs processing by starting to read data from a second position (for example, a trail position) different from the first position. A control unit 204 monitors throughput of data processed by each of the processing units. If the total of the throughput reaches a predetermined data size, the control unit 204 performs control to stop parallel processing performed by the first processing unit 203 and the second processing unit 205. Each of the processing units starts processing data from a different position. Based on progress in each processing, the control unit 204 determines a time point at which the parallel processing of the data is completed. In this way, the processing at the first processing unit 203 and the processing at the second processing unit 205 can be terminated at the same timing.

Description

  The present invention relates to a technique for processing data in parallel by a plurality of arithmetic processing units.

In recent years, digital cameras have increased in the number of pixels, and devices that can process and capture still images with a huge amount of information by processing image data at high speed and devices that can capture still images while recording moving images have been commercialized. Yes.
The image processing is performed while dividing the image data. The captured image data is temporarily stored in a memory and then processed, or the still image divided during moving image capturing and recording is processed sequentially. The method is known. In addition, a method has been proposed in which a plurality of arithmetic processing circuits capable of performing the same arithmetic processing are provided, and parallel processing is simultaneously performed by pipeline processing.
In Patent Document 1, image data to be accumulated in the memory of each arithmetic circuit is assigned so that arithmetic processing by each arithmetic circuit is completed simultaneously in a parallel image processing apparatus that performs arithmetic processing on image data in parallel. Also, in Patent Document 2, divided region data of image data is input to a plurality of input means, and image processing that can be processed independently for each divided region is executed by pipeline processing for each of the input divided region data. The By integrating the pipeline processing results, it is possible to process images divided at high speed in an arbitrary order.

JP 2002-216121 A Japanese Patent Laid-Open No. 10-304184

However, in the techniques of Patent Literature 1 and Patent Literature 2, it is necessary to calculate the divided areas of the image data in advance, and complicated arithmetic processing is required before performing parallel processing.
An object of the present invention is to realize parallel processing of data without requiring complicated arithmetic processing in advance for allocation of divided areas and memory addresses.

  In order to solve the above problem, an apparatus according to the present invention includes a first processing unit that processes data read from a memory, a second processing unit that processes data read from the memory, Control means for processing the predetermined data in parallel by the second processing means while processing the predetermined data stored in the memory by the first processing means. The control means controls the first processing means so as to continuously read and process from the first position in the predetermined data, and continuously reads from the second position in the predetermined data. The second processing means is controlled to process, and the sum of the data amount processed by the first processing means and the data amount processed by the second processing means reaches the predetermined data size. In such a case, the parallel processing by the first processing means and the second processing means is stopped.

  According to the present invention, parallel processing of data can be realized without requiring complicated arithmetic processing in advance for allocation of divided areas and memory addresses.

It is a block diagram which shows the structural example of an apparatus for describing 1st Embodiment of this invention combined with FIG. 2 and FIG. It is explanatory drawing of the example of parallel processing. It is a flowchart explaining the example of parallel processing. It is a flowchart explaining the example of parallel processing in 2nd Embodiment of this invention. It is a flowchart explaining the example of parallel processing in 3rd Embodiment of this invention. It is a flowchart explaining the example of parallel processing in 4th Embodiment of this invention. It is an input-output waveform diagram explaining parallel processing. It is explanatory drawing of the example of parallel processing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The image data processing apparatus will be described as an example, but the present invention can be widely applied to apparatuses that process various data in parallel.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration example of a data processing apparatus according to the first embodiment of the present invention.
FIG. 1A is a diagram illustrating a configuration of an imaging device 100 including a data processing device to which the present invention is applied. In FIG. 1A, an imaging unit 101 captures a subject and outputs image data. The memory 102 stores image data from the imaging unit 101. The image processing unit 103 reads the image data stored in the memory 102, performs a predetermined process, and stores the image data in the memory 102 again. In addition, the image processing unit 103 processes various information displayed on the display unit 104 and stores the information in the memory 102 according to instructions from a CPU (Central Processing Unit) 106.
The display unit 104 displays image data read from the memory 102 and other information. The recording unit 105 records the image data read from the memory 102 on a recording medium such as a memory card. The CPU 106 controls each unit of the imaging apparatus 100 in response to an instruction from the operation unit 107. Further, the CPU 106 controls processing by the image processing unit 103. The clock generation unit 108 generates an operation clock for the imaging apparatus 100. Each unit of the imaging apparatus 100 operates according to the clock from the clock generation unit 108.

  FIG. 1B is a diagram illustrating a configuration example of the image processing unit 103. In FIG. 1B, the image data recorded in the memory 102 is taken into the image processing unit 103 by the first reading unit 200. A part of the image data is read by the first reading unit 200. The image data read by the first reading unit 200 is input to the first processing unit 203 via the input selector 202. The first processing unit 203 includes a processing circuit that performs a predetermined calculation (first calculation process) for image processing. Further, the first processing unit 203 processes the data of each pixel of the image data according to the clock from the clock generation unit 108. The first processing unit 203 includes a counter that counts every time a predetermined amount of image data being processed is processed based on the clock. The predetermined amount is, for example, a data amount corresponding to one line, and the counter counts the number of lines (the count value is described as TC1). TC1 is incremented by 1 each time a value corresponding to the number of pixels for one line in one-screen image data read from the memory 102 is counted. The count value TC1 is output to the control unit 204. The first processing unit 203 sends the processed data (calculation result) to the output selector 206, and the first writing unit 207 outputs the processed data to the memory 102.

Part of the image data stored in the memory 102 is also read by the second reading unit 201. The image data read by the second reading unit 201 is input to the second processing unit 205 via the input selector 202. Similar to the first processing unit 203, the second processing unit 205 that performs the second arithmetic processing includes a processing circuit that performs image arithmetic processing. The second processing unit 205 processes the data of each pixel of the image data according to the clock from the clock generation unit 108. The second processing unit 205 includes a counter that counts the number of lines of image data being processed based on the clock (the count value is denoted as TC2). TC2 increases by 1 each time a value corresponding to the number of pixels for one line in one-screen image data read from the memory 102 is counted. The count value TC2 is output to the control unit 204.
The control unit 204 detects the state of data being processed by each processing unit based on the line count values TC1 and TC2 from the first processing unit 203 and the second processing unit 205. And each processing part is controlled according to the progress state of this process. For example, the control unit 204 monitors the line count values TC1 and TC2 from the first processing unit 203 and the second processing unit 205. By comparing values indicating the line count position in the vertical direction of the image, the end timing of the parallel processing can be detected.

Next, with reference to FIG. 2 and FIG. 3, the setting process and control content of the parallel operation process in this embodiment are demonstrated. FIG. 2 is a diagram for explaining the processing, and FIG. 3 is a flowchart for explaining a processing example. 3 is executed by the CPU 106 and the control unit 204 controlling each unit. Some processing is executed by the image processing unit 103.
In FIG. 3, the control unit 204 sets the start address in the memory 102 of the image data output to the first processing unit 203 and the second processing unit 205 in accordance with an instruction from the CPU 106. The control unit 204 outputs the set read start address to the first read unit 200 and the second read unit 201 (S301). For example, in the present embodiment, it is assumed that the first processing unit 203 performs processing from the top position of image data on one screen, and the second processing unit 205 performs processing from the tail end to the top of one screen. Therefore, the control unit 204 instructs the first reading unit 200 to set the address of the top data in the image data of one screen to be processed as a reading start address, and to perform forward reading. On the other hand, the control unit 204 instructs the second reading unit 201 to set the address of the last data in the image data of one screen to be processed as a reading start address, and to perform backward reading. When the reading start address and the reading order are set in this way, the first reading unit 200 reads image data from the top of one screen toward the back in synchronization with the clock from the clock generation unit 108. On the other hand, the second reading unit 201 reads image data from the last data of one screen toward the top in synchronization with the clock from the clock generation unit 108.

As described above, different reading start positions are set in the first reading unit 200 and the second reading unit 201, and the reading directions are opposite to each other.
In addition, the control unit 204 sets a write start address and a writing direction by the first writing unit 207 and the second writing unit 208. In the present embodiment, the first writing unit 207 and the second writing are performed so that data obtained as a result of processing the image data of one screen by the first processing unit and the second processing unit is stored in the memory 102 at consecutive addresses. Each write start address of the unit 208 is determined. In addition, the control unit 204 instructs the first writing unit 207 to write in the forward direction, and instructs the second writing unit 208 to write in the reverse direction.

  Next, the control unit 204 instructs the first processing unit 203 and the second processing unit 205 to perform parallel processing on the input image data (S302). In addition, the control unit 204 instructs each processing unit also about the contents of the processing. Processed data that is a calculation result by each processing unit is written into the memory 102 through the first writing unit 207 and the second writing unit 208 according to the set start position and direction. Next, the control unit 204 sets the line count value TC1 corresponding to the processing amount of the image data processed by the first processing unit 203 and the line count value TC2 corresponding to the processing amount of the image data processed by the second processing unit 205. get. Based on these count values, the control unit 204 determines whether image data for one screen has been processed by each processing unit (S303). Specifically, it is determined whether or not TC1 + TC2 is equal to C when the number of pixels (number of lines) in the vertical direction of image data for one screen to be processed is denoted as “C”. If it is determined that “TC1 + TC2 = C”, the process proceeds to S304. If it is determined that “TC1 + TC2 <C”, the process returns to S302, and parallel processing by the first processing unit 203 and the second processing unit 205 is performed. The When the processing of the image data for one screen is completed, the control unit 204 stops the processing by each processing unit in S304. That is, the control unit 204 instructs the first processing unit 203 and the second processing unit 205 to stop processing, and instructs the first reading unit 200 and the second reading unit 201 to stop reading, and performs computation. End the process.

In the process of FIG. 3, the first writing unit 207 writes the processed data in the forward direction to the memory 102, and the second writing unit 208 writes the processed data in the reverse direction to the memory 102. Therefore, the calculation end timing is the time when the added value of TC1 and TC2 reaches the C value corresponding to the number of lines of image data.
However, the present invention is not limited to this, and the end timing of the arithmetic processing may be changed in accordance with the arithmetic contents. For example, in the case of computation processing that requires overlap, the time when “TC1 + TC2 = C” is reached is not the completion time of the computation processing. In this case, each calculation process may be completed when a predetermined number of lines of processing (overlap processing) is performed from the time when “TC1 + TC2 = C” is reached. The first processing unit 203 and the second processing unit 205 can perform similar arithmetic processing. For this reason, when the same image processing is executed by these processing units, the image data written in the memory 102 includes the data written by the first writing unit 207 in the forward direction and the second writing unit 208 writing in the reverse direction. Consists of data performed. That is, a process of writing data to the image area of the memory 102 is executed by parallel processing, and an output result similar to that obtained when the input image data is performed by a single arithmetic processing circuit is obtained.

FIG. 2 is a diagram showing an image processed in the present embodiment. In FIG. 2, the passage of time is shown from top to bottom, the left side shows the processing of the first processing unit 203, and the right side shows the processing of the second processing unit 205. P100 indicates image data of one screen to be processed.
During the processing of the image data P100 by the first processing unit 203, the second processing unit 205 reads the image data P100 from the memory 102 from the end (address). Parallel processing is performed by each processing unit performing similar arithmetic processing. The control unit 204 performs the determination process by acquiring the TC value (TC1) of the first processing unit 203 and the TC value (TC2) of the second processing unit 205. When the sum of TC1 and TC2 matches the number of lines of the image data P100, the control unit 204 ends the arithmetic processing of the first processing unit 203 and the second processing unit 205, thereby completing the parallel processing at the same time. Timing is indicated by “T1”). However, either the first processing unit 203 or the second processing unit 205 may be terminated first depending on the timing of the arithmetic processing of both.

In the first embodiment, the parallel processing ends at the time when the sum of the processed areas in the input image data matches the processing size of the entire image data or when the overlap processing of a predetermined amount of data further ends from this time. Each calculation process ends at the same time. Therefore, when image data of one screen is processed in parallel by two processing units, the image data processed by each processing unit can be easily specified. That is, it is not necessary to perform complicated processing for assigning image data processed by each processing unit to a memory area.
The processing described above can also be realized by a computer constituting the image processing apparatus reading out and executing a data processing program from the memory. That is, the CPU (Central Processing Unit) executes the following processing steps according to the description contents of the data processing program. The computer controls the predetermined data stored in the memory to be processed in parallel by the second processing means while the first processing means processes the predetermined data. As for the first processing means, the functions of the first reading unit 200, the first processing unit 203, and the first writing unit 207 are realized by the CPU executing a program. Similarly, the second processing means is realized by the CPU executing the functions of the second reading unit 201, the second processing unit 205, and the second writing unit 208.
In the first process, a step of controlling the first processing means so as to continuously read and process from the first position in the predetermined data is executed. Further, a step of controlling the second processing means so as to continuously read and process from the second position in the predetermined data is executed. For example, the first position is set at the beginning of predetermined data, and the reading direction and the writing direction (first direction) are backward. The second position is set at the end of the data, and the reading direction and the writing direction (second direction) are forward. The CPU executes the first and second processing in parallel processing. Then, the CPU monitors the data processing amount in the first and second processing, and compares the total processing amount with the size of predetermined data. That is, when the sum of the data amount processed by the first processing means and the data amount processed by the second processing means reaches a predetermined data size, a step of stopping parallel processing is executed. . Since it is not necessary to obtain the division area of the input image data in advance by a complicated calculation, the parallel processing capability of the CPU can be increased.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. Since the configuration of the apparatus according to the second embodiment is the same as that of the first embodiment, the detailed description thereof will be omitted by using the same reference numerals already used for the respective components, and the differences will be described below. The point will be mainly described. Note that the method of omitting such description is the same in other embodiments described later.
In the second embodiment, for example, the first processing unit 203 starts processing from the top of image data of one screen, and the second processing unit 205 starts from the middle of image data of one screen. A processing example of this embodiment will be described with reference to the flowchart of FIG.

In FIG. 4, the control unit 204 sets the read address and read direction from the memory 102, and the write address and write direction for the memory 102 (S401). For example, the control unit 204 sets the first processing unit 203 to read in the forward direction from the top of the image data of one screen to be processed. Further, the control unit 204 sets the second processing unit 205 to perform forward reading from a position after a predetermined offset value (OFV) from the top of the image data of one screen to be processed. In the present embodiment, for example, the position of C / 2 that is half the number of pixels (number of lines) C in the vertical direction in the image data of one screen is set as the reading start position. Then, the control unit 204 sets the address of the reading start position in the second reading unit 201. In other words, data is read backward from the position where the OFV is added to the start position of the image data of one screen.
Similarly, the control unit 204 sets a write start address and a write direction of processed data for the memory 102, and outputs them to the first writing unit 207 and the second writing unit 208. Further, the control unit 204 writes the data in order from the top of the image data to the first writing unit 207 so that the image data processed by each processing unit is stored at consecutive addresses in the memory 102. To instruct. The control unit 204 instructs the second write 208 to use an address after the offset value OFV from the write start address set in the first write unit 207 as the write start address.

Next, the control unit 204 instructs the first processing unit 203 and the second processing unit 205 to perform arithmetic processing in parallel (S402). The image data processed by each processing unit is written into the memory 102 by the first writing unit 207 and the second writing unit 208. After the processing is started by each processing unit, the control unit 204 sets the line count value TC1 from the first processing unit 203 and the set value of the reading start position of the image data output to the second processing unit 205. Compare Then, the control unit 204 determines whether or not TC1 is equal to the image data read start position (start position + offset value) for the second processing unit 205 (S403). When it is determined that the two match, the control unit 204 instructs the first processing unit 203 to stop the processing, and ends the arithmetic processing of the first processing unit 203 (S404). Next, based on the value of TC2 from the second processing unit 205, the control unit 204 determines whether the arithmetic processing of the second processing unit 205 has been completed (S405). When it is determined that the arithmetic processing of the second processing unit 205 has not been completed, the arithmetic processing by the second processing unit 205 is continued (S406).
In S403, when the TC1 and the reading start position of the image data by the second processing unit 205 do not coincide with each other, the control unit 204 determines whether or not the processing of the second processing unit 205 is finished (S407). Here, the end of the process of the second processing unit 205 is determined by determining whether the data processed by the second processing unit 205 is the last line of one screen. If the calculation processing of the second processing unit 205 has not ended in S407, the process returns to S402, and the parallel processing by the first processing unit 203 and the second processing unit 205 is continued.
If the processing of the second processing unit 205 has not ended in S407, the control unit 204 and the line count value TC1 from the first processing unit 203 and the image data output to the second processing unit 205 are displayed. Compare the set value of the read start position. Then, the control unit 204 determines whether or not TC1 is equal to the image data reading start position for the second processing unit 205 (S408). When it is determined that the two match, the control unit 204 instructs the first processing unit 203 to stop the processing, and ends the arithmetic processing of the first processing unit 203 (S409). If the two do not match, the control unit 204 continues the processing by the first processing unit 203 (S410). Then, the process returns to S408.

As described above, the calculation processing start positions by the plurality of processing units are set to different positions, and data is read and written according to the same direction (from the head to the rear in the above example). The end point of the process is determined based on the offset value used when setting the start position to a different position.
According to the second embodiment, the completion position of the first arithmetic processing by the first processing unit 203 is set to the start position in the middle of the image data, and the first processing unit 203 determines that the TC value of the processed data is The process is completed when the position is reached. If the processing of the second processing unit 205 has been completed up to this point, the completion timing of the processing of the image data for one screen coincides with the end point of the processing of the first processing unit 203. Therefore, it is not necessary to obtain a divided region of the input image by complicated calculation, and the image data can be processed in parallel by a plurality of calculation processing units.
In the second embodiment, the second processing unit 205 starts the arithmetic processing from the second position while the first processing unit 203 performs the arithmetic processing from the first position, for example, from the top of the data. Thereby, the start position of the arithmetic processing by the second processing unit and the processing progress of the arithmetic processing of the first processing unit are compared, and the timing for ending the parallel processing can be determined. That is, with respect to the completion timing of the parallel processing, the position of the data processed by the first processing unit 203 reaches the second position where the calculation processing of the second processing unit 205 is started from the middle of the data. It can be set.

[Third Embodiment]
Next, a third embodiment of the present invention will be described.
The first and second embodiments have been described on the assumption that both the first processing unit 203 and the second processing unit 205 perform parallel processing from the beginning. In the third embodiment, a plurality of arithmetic processing units process different data, and after a certain processing unit finishes the arithmetic processing, an example of assisting processing performed by another processing unit. explain.
FIG. 8 shows an example of arithmetic processing of the first processing unit 203 and the second processing unit 205. The passage of time is shown from top to bottom, the left side shows the processing of the first processing unit 203, and the right side shows the processing of the second processing unit 205. Image data P200 and P201 indicate processing targets of the first processing unit 203, and image data P202 to P206 indicate processing targets of the second processing unit 205.

  First, the first processing unit 203 and the second processing unit 205 each process different image data. It is assumed that the first processing unit 203 starts processing the image data P201 next after finishing the processing of the image data P200. At a certain time, the second processing unit 205 finishes the processing of the image data P202 to P206 first. The second processing unit 205 performs parallel processing to assist the arithmetic processing during the processing of the image data P201 by the first processing unit 203. In this case, a period during which a plurality of processing units perform parallel processing on the same image data (hereinafter referred to as a parallel processing period) and a period during which each processing unit processes different image data (hereinafter referred to as an individual processing period). It is necessary to distinguish. Based on the processing states of the first processing unit 203 and the second processing unit 205, the CPU 106 generates a determination signal (hereinafter referred to as a MODE signal) for the parallel processing period and the individual processing period of each processing unit, and the image processing unit To 103.

With reference to the flowchart of FIG. 5, the processing of the image data in this embodiment will be described.
First, the CPU 106 determines whether or not to process image data for one screen in parallel based on the contents processed by the first processing unit 203 and the second processing unit 205, and sets the value of the MODE signal. The MODE signal takes a value of 0 or 1. For example, when the first processing unit 203 and the second processing unit 205 process different image data in parallel (hereinafter referred to as parallel processing A), or when only one of the processing units performs arithmetic processing, The value of the MODE signal is set to 0. Further, when the first processing unit 203 and the second processing unit 205 perform parallel processing on a part of the same image data of one screen (hereinafter referred to as parallel processing B), the value of the MODE signal is set to 1. In this embodiment, since it is assumed that different image data is first processed by the first processing unit 203 and the second processing unit 205, 0 is set as the value of the MODE signal.

Next, the control unit 204 determines the value of the MODE signal (S502). When the value of the MODE signal is 0, the control unit 204 causes the first processing unit 203 and the second processing unit 205 to execute processing set by the CPU 106 (S507). At this time, the control unit 204 receives, from the CPU 106, information on an address where image data to be processed for each processing unit is stored in the memory 102. The control unit 204 instructs the first reading unit 200 and the second reading unit 201 to read the image data to be processed. The calculation results by the respective processing units are stored in the memory 102 by the first writing unit 207 and the second writing unit 208, respectively.
Next, the control unit 204 determines whether or not the arithmetic processing of the first processing unit 203 and the second processing unit 205 has ended (S508). When the arithmetic processing by both processing units is completed, the processing ends. If one of the arithmetic processes has not ended, the control unit 204 determines whether one of the first processing unit 203 and the second processing unit 205 has ended (S509). ). If neither calculation process is completed, the process returns to S507 and the process is repeated. If either one of the calculation processes is completed, the process returns to S501. When one of the processes is completed in this way, the control unit 204 notifies the CPU 106 to that effect. The CPU 106 sets the MODE signal to 1 when the processing of one processing unit is completed.

When the MODE signal is set to 1, the control unit 204 causes one of the first processing unit 203 and the second processing unit 205 to process the image data of one screen being processed also in the other processing unit. Therefore, for example, in the memory 102, the control unit 204 sets the data address at the end of the image data of one screen processed by the first processing unit 203 in the second reading unit 201 as a reading start address. Further, the control unit 204 instructs the second reading unit 201 to read the image data in the reverse direction (S503). Therefore, as in the first embodiment, during the processing of the image data by the first processing unit 203, the second reading unit 201 reads the image data in the reverse direction from the end portion of the same image data, and the second processing. Processed by the unit 205 (parallel processing B).
Thus, the image data read start position of the second processing unit 205 is set to the last position of the image data processed by the first processing unit 203. Similarly, the writing start address of the second writing unit 208 is set to an address one screen after the writing start address of the image data processed by the first processing unit 203 to the memory 102, and writing is performed in the reverse direction. Is set as follows.

  In next step S504, the control unit 204 instructs the first processing unit 203 and the second processing unit 205 to process the respective input image data in parallel in the arithmetic processing. Each calculation result is written into the memory 102 by the first writing unit 207 and the second writing unit 208. Next, the control unit 204 acquires the TC1 value of the first processing unit 203 and the TC2 value of the second processing unit 205. Then, it is determined whether or not TC1 + TC2 is equal to the number C of pixels in the vertical direction of the image data of one screen to be processed (S505). When it is determined that “TC1 + TC2 = C”, the control unit 204 outputs a processing end signal to the first processing unit 203 and the second processing unit 205, and ends the respective arithmetic processing (S506). If it is determined in S505 that TC1 + TC2 is not equal to C, the process returns to S504 and the process is continued. This completes the parallel processing. In addition, since it is as having demonstrated in 1st Embodiment when overlap processing is required, the description is abbreviate | omitted.

Next, the end timing when parallel processing is performed will be described with reference to FIG. FIG. 7 shows the state of data processed by each processing unit. Data is input when each is in a high level state. The input waveform (1) is a waveform of input data indicating the processing target of the second processing unit 205, and the input waveform (3) is a waveform of input data indicating the processing target of the first processing unit 203. The output waveform (2) is an output waveform of data calculated by the second processing unit 205, and the output waveform (4) is an output waveform of data calculated by the first processing unit 203.
The upper part of FIG. 7 shows an input / output waveform example when the first processing unit 203 and the second processing unit 205 process only different image data (parallel processing A). In this example, the second processing unit 205 processes the input waveform (1) from the memory 102 and writes the data indicated by the output waveform (2) in the memory 102. In parallel with this, the first processing unit 203 processes the input waveform (3) from the memory 102 and writes the data shown in the output waveform (4) in the memory 102. The time when the arithmetic processing of the first processing unit 203 ends (see T2) is the timing of completion of the processing.

The lower part of FIG. 7 shows an input / output waveform example related to the case where the first processing unit 203 and the second processing unit 205 process the same image data (parallel processing B). In this example, the arithmetic processing of the second processing unit 205 ends first. As indicated by the hatched portion 701 in the input waveform (1) of the second processing unit 205, the unprocessed portion of the data of the input waveform (3) being processed by the first processing unit 203 is the second processing unit 205. It becomes a new processing target. That is, the second processing unit 205 reads unprocessed image data forward from the last position and executes parallel processing. Thereby, the 1st processing part 203 and the 2nd processing part 205 can be ended simultaneously. The process completion timing is a time point (see T1) when both the processing units finish the arithmetic process at the same time, and is before T2.
In this way, by determining the value of the MODE signal and switching between the parallel processing A and the parallel processing B by the plurality of arithmetic processing units, the processing efficiency is improved. In the example of FIG. 7, the process in which the second processing unit 205 assists the first processing unit 203 after the end of the arithmetic processing has been described. However, the present invention is not limited to this. For example, even when the first processing unit 203 and the second processing unit 205 are processing different image data and switched to the parallel processing B, the processing can be ended simultaneously.

FIG. 8 is an explanatory diagram visually illustrating the input / output waveforms illustrated in the lower part of FIG. 7 as an image. For example, it is assumed that the first processing unit 203 processes image data P200 and the second processing unit 205 processes image data P202 to P206.
After finishing the processing of the image data P200, the first processing unit 203 starts to process the image data P201. On the other hand, the second processing unit 205 sequentially processes the image data P202 to P206, and when the processing of the image data P206 is finished, the first processing unit 203 is in the process of processing the image data P201. is there.
If the value of the MODE signal is set to 1 during the processing of the image data P201 by the first processing unit 203, the second processing unit 205 reads the image data P201 from the tail and reads it forward, to the memory 102. Perform reverse writing of. When the value of the MODE signal is set to 1, the control unit 204 acquires the TC values of the first processing unit 203 and the second processing unit 205, and the sum (TC1 + TC2) and the vertical direction of the image data P201. The number of pixels (C) is compared. If the two match, the control unit 204 ends the arithmetic processing of the first processing unit 203 and the second processing unit 205, so that the parallel processing B is completed at the same time (see T1). However, depending on the timing of both computation processes, either one may be terminated first.

In the third embodiment, the period during which the parallel processing B is performed can be determined by setting the value of the MODE signal. Therefore, even when a certain processing unit is processing from the beginning of the data, another processing unit can process from the back of the data. Since the parallel processing B ends when the total size of the areas where the mutual data processing is completed matches the processing amount of the entire data or after the overlap processing, it is possible to improve the calculation processing efficiency.
According to the third embodiment, it is determined whether or not it is a parallel processing period, that is, a state in which a plurality of arithmetic processing units respectively process different data in parallel, and the same data is processed in parallel. The state can be determined. For this reason, during the parallel processing period, the control unit can grasp whether or not parallel processing is completed at the same time by observing data in a memory area that has already been processed by each processing unit.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, a plurality of arithmetic processing units process different data, and after a certain processing unit finishes the arithmetic processing, an example of assisting processing performed by another processing unit. explain. For example, when the second processing unit 205 finishes processing while the first processing unit 203 is executing processing from the beginning of the data, the processing is started from an intermediate position of the image data. The first processing unit 203 can be assisted by causing the second processing unit 205 to share unprocessed data.

A processing example according to the present embodiment will be described with reference to the flowchart of FIG. In addition, each process shown to S601-S602 and S608-S610 in FIG. 6 is respectively the same as the process of S501-S502, S507-S509 of FIG. Therefore, description of those processes is omitted, and S603 to S607 will be mainly described below.
If the value of the MODE signal is 1 in S602, the process proceeds to S603. The control unit 204 processes the image data of one screen being processed by one processing unit, here the first processing unit 203, in parallel by the second processing unit 205. Set the reading direction. Further, the control unit 204 sets a write address and a write direction of the second writing unit 208 (S603). Here, the control unit 204 is positioned after the TC1 by the first processing unit 203 at that time and a position (offset) after the predetermined value from the top of the image data of one screen processed by the first processing unit 203. Value) is set as the reading start position. Furthermore, the control unit 204 sets the reading direction to read in the forward direction toward the rear of the image data of one screen being processed. In addition, the control unit 204 sets a value obtained by adding the offset value set by the second reading unit 201 to the writing start position of the first writing unit 207 as a writing start address, and outputs it to the second writing unit 208.

  Next, the control unit 204 causes the first processing unit 203 and the second processing unit 205 to process the image data in parallel (S604). Next, the control unit 204 compares the TC1 from the first processing unit 203 with the set value of the reading start position of the second processing unit 205 (S605). If it is determined that the two do not match, the process returns to S604 and is repeated. If it is determined that the two match, the control unit 204 transmits a processing end signal to the first processing unit 203 to stop the arithmetic processing (preceding processing) of the first processing unit 203 and to that effect. Is notified to the CPU 106 (S606). When the processing of the first processing unit 203 ends, the value of the MODE signal is set to 0. Next, the control unit 204 determines whether or not the processing of the second processing unit 205 has been completed (S607). If the processing of the second processing unit 205 is not completed, the process proceeds to S608, and the arithmetic processing is repeatedly executed. If it is determined in S607 that the processing of the second processing unit 205 has been completed, the series of processing ends.

  In the fourth embodiment, the period during which the parallel processing B is performed can be determined by setting the value of the MODE signal. Therefore, even when a certain processing unit is processing from the beginning of the data, another processing unit can process from the middle stage of the data. By comparing the start position of the processing unit that performs processing from the middle stage with the TC value of the preceding processing unit that is processing data from the beginning, the control unit can grasp the processing progress. The parallel processing B ends when the TC value of the preceding processing unit matches the start position of the processing unit that performs processing from the middle stage. In this way, the processing completion timing can be set to the start position of the data to be input and processed in the subsequent processing unit that performs the arithmetic processing from the middle stage.

As described above, according to the fourth embodiment, for example, a data portion unprocessed by the first processing unit can be shared by the second processing unit. In other words, parallel processing can be executed by assisting data held by any one of the plurality of arithmetic processing units without being processed by another arithmetic processing unit.
In each of the above-described embodiments, the case where there are two arithmetic processing units having the same processing capability has been described as an example, but the number of arithmetic processing units may be three or more. Further, the control unit 204 has described the case where the TC values are compared.

200 First Reading Unit 201 Second Reading Unit 203 First Processing Unit 204 Control Unit 205 Second Processing Unit 207 First Writing Unit 208 Second Writing Unit

Claims (8)

First processing means for processing data read from the memory;
Second processing means for processing data read from the memory;
Control means for processing the predetermined data in parallel by the second processing means while processing the predetermined data stored in the memory by the first processing means;
The control means controls the first processing means so as to continuously read and process from the first position in the predetermined data, and continuously reads from the second position in the predetermined data. The second processing means is controlled to process, and the sum of the data amount processed by the first processing means and the data amount processed by the second processing means reaches the predetermined data size. In such a case, the data processing apparatus stops parallel processing by the first processing means and the second processing means.   The control means sets the first position in the predetermined data as the first position and reads the predetermined data continuously from the first position toward the end. The second process so as to control the means to set the last position in the predetermined data as the second position and to continuously read out the predetermined data from the second position toward the head. The data processing apparatus according to claim 1, wherein the means is controlled.   The control means sets the first position in the predetermined data as the first position and reads the predetermined data continuously from the first position toward the end. And a predetermined position in the middle of the predetermined data from the beginning to the last position is set as the second position, and the predetermined data is continuously moved from the second position toward the last. The data processing apparatus according to claim 1, wherein the second processing unit is controlled to read out the data. Each of the first processing means and the second processing means has a counter that counts each time a predetermined amount of data is processed,
The control means controls timing for stopping parallel processing of the first and second processing means based on the count values of the counters from the first processing means and the second processing means. The data processing device according to claim 1, wherein the data processing device is a data processing device.   The control means is preset when the position of the data being processed by the first processing means and the position of the data being processed by the second processing means match or are set in advance from the matching positions. 5. The data processing apparatus according to claim 4, wherein when the processing of the data amount is completed, the parallel processing by the first and second processing means is stopped.   When the second processing unit finishes processing the data different from the predetermined data while the first processing unit is processing the predetermined data, the control unit The data that is not processed by the first processing means among the data is processed by the second processing means in parallel with the processing of the predetermined data by the first processing means. The data processing device according to any one of 1 to 5. First processing means for processing data read from the memory;
Second processing means for processing data read from the memory;
Control executed by a data processing apparatus provided with control means for processing the predetermined data in parallel by the second processing means while processing the predetermined data stored in the memory by the first processing means A method,
By the control means,
Controlling the first processing means to continuously read and process from a first position in the predetermined data;
Controlling the second processing means to continuously read and process from a second position in the predetermined data;
When the sum of the data amount processed by the first processing means and the data amount processed by the second processing means reaches the predetermined data size, the first processing means and the second processing means A method for controlling a data processing apparatus, comprising the step of stopping parallel processing by a processing means. First processing means for processing data read from the memory;
Second processing means for processing data read from the memory;
The predetermined data stored in the memory is processed by the first processing means, and is executed by a computer in a data processing apparatus provided with a control means for processing the predetermined data in parallel by the second processing means. A data processing program,
By the control means,
Controlling the first processing means to continuously read and process from a first position in the predetermined data;
Controlling the second processing means to continuously read and process from a second position in the predetermined data;
When the sum of the data amount processed by the first processing means and the data amount processed by the second processing means reaches the predetermined data size, the first processing means and the second processing means A data processing program comprising a step of stopping parallel processing by a processing means.

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