JPH0728991A - Data processing circuit using memory - Google Patents

Abstract

PURPOSE:To make the scale of a circuit small, to improve the degree of freedom and to perform processing of pictures at a high speed by accessing a memory decided by addresses in plural directions orthogonally crossing with each other by the addresses generated by plural specific counters. CONSTITUTION:At the time of accessing a picture memory 6 of a bit map form and performing the read/write processings of data, table memories 3 and 4 provided with at every horizontal and vertical direction are addressed by the count values of a dot counter 1 and a line counter 2 for performing count up/down in synchronism respectively with clot clocks and line clocks and output access addresses in the horizontal and vertical, directions of the picture memory 6. The data of address tables constituted of the address memories 3 and 4 are loaded to the respective memories 3 and 4 by an address generation means 5 at every input of the conditions of trimming or the like. The address inside the picture memory 6 is specified by the access addresses outputted from the memories 3 and 4 and the read/write of the data are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing circuit using a memory, and in particular, in a photographic film trimming device or the like, various processing is applied to original image data so that the image can be enlarged, reduced or rotated freely. It relates to a data processing circuit suitable for use in performing.

[0002]

2. Description of the Related Art In order to obtain a desired photograph by trimming an original image of a developed photographic film, a clerk instructs the trimming condition at a photo print shop or the like, and the clerk prints the photograph in the store. The current situation is to use the machine, or to ask a photo processing factory that integrates the area called a core lab to perform trimming with a dedicated photo printing machine.

[0003]

All of these apparatuses perform optical trimming and print on photographic paper, and have a limited range of adjustment such as color and gradation, and a plurality of them. A great deal of work is required to combine film images and characters. In addition, since the customer does not operate by himself, it is difficult to obtain the print intended by the customer.

In addition, the customer operates by himself to enlarge or reduce,
Although a device for rotating and trimming has been developed,
After all, it is a type that performs optical processing, and therefore, processing with a high degree of freedom cannot be performed.

If a photographic film is converted into a digital signal by a scanner, image processing is performed on a computer, and then printing is performed by a color printer, gradation and color adjustment,
It is possible to easily perform processing with a high degree of freedom, such as combining a plurality of images and combining characters. However, in such a system, the amount of calculation is large and a long processing time is required to perform enlargement, reduction, rotation, etc. by software on a computer.

The present inventor has improved the above-mentioned current situation and installed a small trimming device individually in a camera shop or the like so that a customer can perform trimming by inputting desired conditions from a keyboard or the like. Then, various studies were made on the realization of a small-sized, high-speed trimming device (hereinafter referred to as a stand-alone type trimming device) that can withstand practical use.

A schematic of the device considered is shown in FIG. The apparatus main body includes a keyboard 2000, a scanner section 2500, a trimming processing section 3000, and a printer 4000, and obtains a desired print 5000 using the negative film 1000 as an original image.

As a result of such various studies, the following problems have become clear. A stand-alone trimming device requires high-speed processing to improve throughput. In order to cope with this increase in speed and to freely perform enlargement, reduction, mirror image inversion, etc., large-scale hardware is required, and the device becomes large.

Although processing by software (processing that is not so complicated) can be performed by using software, it takes time. Further, if processing for image quality improvement such as moire prevention processing is performed, it takes more time.

The present invention has been made based on such a consideration, and its purpose is to provide a small-scale circuit with a high degree of freedom (enlargement, reduction, mirror image conversion, 90 ° rotation, etc.). ) And realizing a data processing circuit that enables high-speed image processing (and thus realizing the above-mentioned stand-alone trimming device).

[0011]

The constitution described in claims 1 to 11 will be outlined below with reference to the drawings. (1) Claims 1, 2, 3 (FIG. 1) As shown in FIG. 1, when accessing the image memory 6 in the bitmap format to perform a data read process or a data write process, an up / down counter (simply, Counter that increments or decrements by 1)
A combination of extremely simple hardware 1 and 2 and an address table composed of address table memories 3 and 4 (table data can be generated with relatively simple software, and the software load associated with data generation is small). The mechanism generates an access address.

The table memories 3 and 4 are provided for each of the horizontal and vertical directions. The dot counter 1 counts up (down) in synchronization with the dot clock, and the line clock (for one row of the memory). Access clock address of the image memory 6 in the horizontal and vertical (x, y) directions, which is addressed by the count value of the line counter 2 which counts up (down) in synchronism with the first clock of one pixel Is output.

Each of the horizontal and vertical address table memories 3 and 4 has a register-type address corresponding to the count value of the counters 1 and 2 on a one-to-one basis, as illustrated in FIGS. It is a RAM that stores a table.

The address table data is generated by the address generating means 5 by the software installed in accordance with the conditions each time a condition such as trimming is input, and loaded into the address table memories 3 and 4.

After the loading is completed, the counters 1 and 2 start counting from a predetermined count value, the address is addressed by this count value, the access address is output from the table memories 3 and 4, and the address in the image memory 6 is changed. The data is read / written at the designated address.

(2) Claim 4 (FIG. 5) At least one of the two horizontal and vertical processing paths,
The switching circuit A is inserted so that the processing paths can be crossed.

(3) Claims 5 and 6 (FIGS. 9 and 10) First using the counter and table memory shown in FIG.
Address generation circuit 60 (generates addresses x and y)
In addition to the above, a second address generation circuit 70 (generating addresses x'and y ') including arithmetic processing circuits 71 and 72 is provided, and high-speed memory access and the like, which has been conventionally difficult, are performed. It is something that can be executed.

(4) Claim 7 (FIG. 11) According to the configuration of this claim, for example, regarding address generation in the horizontal direction, first and second address table memories are provided, and different data are loaded in each memory. , It is possible to intentionally scramble the data (break the periodicity and mix the data) by alternately using the first and second address table memories in the actual address generation stage. There is.

(5) Claims 8 and 9 (FIGS. 15 and 17) In the above-mentioned structure, the method of accessing the image memory 6 is a problem, but in this claim, the output data from the image memory 6 is However, the processing is performed. That is, it is considered that the flow of pipeline data processing is not interrupted when the access to the image memory 6 is completed, but is further extended to the transmission path of the output image data, and the processing stage ( A processing circuit) is arranged to perform a predetermined process, and a desired function is realized by the series of the whole process.

As a specific example, there is an example (FIG. 15) of changing the spatial frequency by further filtering the data output from the image memory 6 with the spatial filter 10. In this case, the filter coefficient (shape of the filter) of the spatial filter 10 is also updated at the same time as the table contents of the address table memories 3 and 4 are rewritten according to conditions such as trimming.

As the processing using the spatial filter, for example, processing such as smoothing and edge enhancement by the convolution calculator 130 as shown in FIG. 17 can be considered. (6) Claim 10 (FIG. 18) The configuration of FIG. 11 (a configuration having a plurality of horizontal address tables, which are used by alternately switching) and the configuration of FIG. 15 (processing for data output from the image memory 6 This is an example of a combination with a configuration having a spatial filter).

(7) Claim 11 (FIG. 19) The basic type of FIG. 1 is used for the data transfer process between memories. That is, the image memory 6a which is the transfer source and the image memory 6b which is the transfer destination are accessed using the address table memories 300 and 400 and 301 and 401.

(8) Claim 12 (FIG. 22) According to the structure of this claim, a CPU 700 that controls the entire system to which the present invention is applied (for example, a photographic film trimming device), and this CPU 700. By using a plurality of memories (6a, 6b, 500) managed by, the data transfer between the memories using the address table memory described above is performed.

(9) Claim 13 (FIG. 25) The above technical concept is applied to a photographic film trimming device.

[0025]

[Action]

(1) Claims 1, 2 and 3 (FIG. 1) The access address is not directly obtained by software for the entire storage area of the memory, but the address circuit is not entirely hardened.
That is, flexible access to the image memory is possible by the combination of the minimum effective software (address table, that is, the software for generating the address table data) and the minimum hardware such as the up / down counter. I am trying.

In other words, taking the write access to the image memory as an example, if the data in the table memories 3 and 4 are set as shown in the right side of FIGS. Each number of indicates the address), as well as normal data write to any address, left-right mirror image conversion,
It is possible to easily perform data writing accompanied by processing such as change of writing position and reduction of 1/2 by thinning. After such writing, if the data is read and printed as it is, a trimmed image can be obtained.

To generate the horizontal and vertical address table data, it is necessary to perform processing according to software in the address generation circuit 6, but horizontal and vertical (x,
It is only necessary to calculate each address of y) independently, the load of software is lighter than in the past, flexible address generation is possible, and speeding up is possible.

After the generated address data is loaded into the table memories 3 and 4, only sequential addressing by the counter is required, and extremely high speed image memory access can be realized.

(2) Claim 4 (FIG. 5) By intersecting the horizontal and vertical paths, as shown in FIG. 6, the image is rotated by 90 ° or 270 ° (that is, such rotation). Access to the image memory) is easily performed.

(3) Claims 5 and 6 (FIGS. 9 and 10) One of the essential features of the present invention is that the number of independent variables corresponding to the address variables (x, y) required for memory access is independent. That is, the signal processing paths are formed in parallel, the paths are synchronized with each other, and the data actually flows like a pipeline.

Therefore, in this claim, the pipeline-like property is used for address generation. That is, a new stage for generating the second address is directly connected to a stage subsequent to the stage for generating the first address, and the address data output from the address tables 3 and 4 is further added to the basic structure of FIG. , A new process called arithmetic process is performed to generate a final access address.

In this case, the address table memory 3,
The data processing 4 is loaded (updated) and the arithmetic processing circuit 7
Flexible data processing is realized by appropriately changing the calculation coefficients of 1,72.

The updating of the data in the table memory and the updating of the calculation coefficient are executed by the address generating circuit 5 and the coefficient generating circuit 80, respectively, as shown in FIG. Is processing by software. Consider the software burden in this case. According to this configuration, the complicated address calculation involving rotation etc. is not executed all at once, but is executed by dividing it into a basic first stage and an applied second stage. However, only the coefficients and the like necessary for the processing of each stage may be calculated independently prior to the data transfer, and software calculation is not required during the data transfer.

Further, since the processing of each stage is executed one after another in the pipeline, it is possible to perform the same multiple processing as the so-called "pipeline processing" in the computer field, and it is possible to speed up the processing.

(4) Claim 7 (FIGS. 11 and 14) According to the configuration of this claim, the effect as shown in the lower right of FIG. 14 can be obtained. In other words, the upper left is the original image data (has periodicity), and if this original image data is accessed using only one address table memory and written with 1.5 times enlargement processing, , The periodicity of the original image and the periodicity of the enlargement process interfere with each other as in the case of the lower left, and the image quality deteriorates due to the occurrence of moire.

In such a case, by switching the address table and varying the access addresses,
It is possible to remove the periodicity of the image and suppress the deterioration of the image quality due to moire.

(5) Claims 8 and 9 (FIGS. 15 and 17) The data output from the image memory 6 can be further filtered. This configuration achieves reduction of moiré and the like by changing the filter characteristics in accordance with the magnification, particularly when the image is enlarged or reduced.
This is important because it can improve the image quality.

Further, by using it in combination with the above-mentioned flexible access to the image memory 6, it is possible to easily perform various kinds of processing including processing for improving image quality such as smoothing and edge enhancement in addition to reducing moire. .

(6) Claim 10 (FIG. 18) By combining flexible memory access and filtering processing, it is possible to perform various processing including processing such as moire prevention which has been difficult in the past.

(7) Claim 11 (FIG. 19) According to the configuration of this claim, it is considered that a series of data processing flows continues until the data read from one memory is written to another memory. The technical idea of is applied. This makes it possible to implement data transfer processing between various memories.

(8) Claim 12 (FIG. 22) According to the structure of this claim, the present invention can be applied not only to the local memory-to-memory transfer but also to the data transfer of the entire system. Can be expanded. in this case,
Since the common bus of the system is used, a dedicated bus connecting each memory is unnecessary, and the configuration is simplified.

(9) Claim 13 (FIG. 25) By applying the above-mentioned technical idea, it is possible to realize a stand-alone type photographic film trimming device which has been conventionally said to be difficult.

[0043]

Embodiments of the present invention will now be described with reference to the drawings. (Embodiment 1) FIG. 3A is a diagram showing a configuration of an embodiment (specific example) of the basic type shown in FIG. 1, and FIG. 3B is a timing chart of each part showing an operation example thereof. is there.

The apparatus of this embodiment is based on the interface circuit 1
The image processing apparatus is used by being connected to the scanner 14 and the printer 15 via the controller 3, and its operation is controlled by the controller 10 as a whole.

The address table memories 3 and 4 are SRA
When the image processing conditions are input from the outside,
The controller 10 calculates the address in each of the horizontal / vertical directions and writes it in the address table memories 3 and 4. After that, this table is addressed by the counter, an access address is generated, and the image memory 6 is accessed.

FIG. 4A is a diagram showing a detailed example of a circuit around the address table memory 3 in FIG. 3, and FIG. 4B is a table when the table is set in the address table 3 and its setting. It is a figure which shows the state etc. of the control signal of the controller 17 at the time of the actual access using the table shown in the table form.

(Embodiment 2) FIG. 7 is a diagram showing the construction of an embodiment (specific example) of the construction (applied type 1) shown in FIG. In this embodiment, the selectors 40 to 43 can be used to switch between the dot clock and the line clock supplied to the horizontal counter 30 and the vertical counter 31.

FIGS. 8A to 8C are views for explaining the effect of this embodiment. Assuming that the image shown in (a) of (a) is read by the scanner in the direction shown in the figure, the address table is set as shown in (b), and the normal write access ( That is,
When the horizontal counter is counted for each pixel and the vertical counter is counted for each line), an image like (c) can be written.

On the other hand, when the setting as shown in (b) and the updating of the counter are executed, the image can be rotated by 90 ° to be written, and the setting as shown in (c) and the updating of the counter. Then, the image can be rotated by 270 ° and written.

(Embodiment 3) FIG. 10 (a) is a diagram showing an embodiment (concrete example) of the configuration of FIG. 9, FIG. 10 (b) is a diagram showing the effect of this embodiment, and FIG. 8] is a diagram showing setting contents of an address table.

In this embodiment, a rectangular region obtained by rotating the x and y axes about the origin by an arbitrary angle, which has been considered to be very difficult in the past (the region indicated by reference numeral K in FIG. 10B). ) Is a very important embodiment in that it enables high-speed access. Rectangular area K in FIG.
Is θ = tan ⁻¹ (−a / b) with respect to the x-axis, θ
It is an area that is only inclined.

In order to access this rectangular area with x0 (= c) as the origin, the arithmetic coefficients a, b, c, d, e (if necessary) given to the arithmetic processing circuit 90 of FIG. f) is as follows. a = cos θ, b = −sin θ, c = x0, d = sin
θ, e = cos θ (however, a = e, b = −d) Further, when x0 = c = 0, access is performed with f as the center. When accessing a coordinate system obtained by rotating the Cartesian coordinate system (x, y coordinate system) by arithmetic processing, if the lower data of the arithmetic result is ignored by data rounding, an error occurs and the calculated coordinate value is It overlaps,
Access may be disturbed. Therefore, when accessing all the pixels in the rectangular area, it is necessary to make the increment of the value set in the address table sufficiently small and execute the finer access.

(Embodiment 4) FIG. 12A is a diagram showing an embodiment (configuration of a concrete example) of FIG. 11, and FIG. 12B is a diagram showing an example of setting an address table. In addition, FIG.
6 is a timing chart showing an operation example of the present embodiment.

In the present embodiment, it is assumed that the image (source image) read by the scanner shown in the upper left of FIG. 14 is magnified 1.5 times and written in the image memory 6.
In a normal light, as shown in the lower left of FIG. 14, the periodicity of the original image interferes with the periodicity of the enlargement process, and the image quality deteriorates.

Therefore, in the configuration shown in FIG. 12A, the selector 19 causes the horizontal address table memories 3a and 3b to operate.
Are alternately switched for each pixel, and the periodicity is dispersed by scattering the image to suppress the generation of moire. This makes it possible to obtain an image that is easy to see, as shown in the lower right part of FIG.

(Embodiment 5) FIG. 16 (a) is a diagram showing the configuration of the applied embodiment of FIG. 15, and FIG. 16 (b) shows the transfer source (source) and transfer destination (destination) of this embodiment. The figure which shows the relationship of an image, (c) is a figure which shows the content of a table, and the example of a convolution coefficient.

In this embodiment, the image memory 150 (source)
Between the image memory 160 and the image memory 160 (destination) during data transfer accompanied by a 1/2 reduction process, 3 ×
The convolution calculation unit 130 of No. 3 filters transfer data to reduce moire.
However, the present embodiment is not limited to data transfer between memories,
It is of course applicable to a mode in which one memory is accessed and the data output as a result is processed.

Like the counters 1 and 2, the convolution operation unit 130 operates in synchronization with the dot clock and the line clock, and does not disturb the flow of the entire data transfer processing (that is, the pipeline disturbance). Is easy to implement.

FIG. 17 shows the convolution calculator 13.
It is a figure for demonstrating the content of 0. As shown in the figure, the convolution calculator 130 includes three stages of flip-flops 131 and the same number of coefficient holding registers 132.
And the same number of multipliers 133 and a circuit 134 for calculating the sum of multiplication results.

According to the present embodiment, by changing the frequency characteristic of the spatial filter according to the enlargement / reduction ratio of the image, moire can be reduced and the image quality can be improved. (Embodiment 6) FIG. 20 is a diagram solely showing a mode in which the present invention is applied to data transfer between memories. Figure 21
(A) and (b) respectively show conditions of a transfer source (source) and a transfer destination (destination) in the case of data transfer accompanied by double expansion and 1/2 contraction in the present embodiment. FIG.

(Embodiment 7) FIG. 23A is a diagram showing the configuration of an embodiment (specific example) of the applied type 7 of FIG. 22, and FIG.
It is a timing chart which shows the example of the operation. In the present embodiment, since the memories connected to the common bus of the system are used, it is not necessary to connect the memories with a dedicated bus, and the arrangement of the buses is simplified.

Further, a register 500 for temporarily holding image data is used as a memory, and the image memory 6a (6b) is used.
Data can be stored in this register once and then returned to the image memory from which the data has been read out again. By doing so, the image position can be changed within one image as shown in FIG. You can also

When two or more image memories are used, if the type of the image memory is indicated by the upper bits of the vertical (or horizontal) address table, the source and destination can be freely set without limitation. A high degree of transfer is possible.

[0064]

As described above, according to the present invention,
A small-scale circuit with a high degree of freedom (that is, writing, reading position is arbitrary, vertical and horizontal independent settings, enlargement, reduction, mirror image conversion, 180 ° rotation, spatial filtering, etc.) and high-speed data ( Image data) can be processed.

As a result, a stand-alone photographic film trimming device can also be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a basic type of the present invention.

2A to 2D are diagrams for explaining the effect of the example of FIG.

3A is a diagram showing the configuration of the basic embodiment of FIG. 1, and FIG. 3B is a timing chart showing an operation example thereof.

4A is a diagram showing a configuration of a peripheral circuit of the address table memory 3 in the configuration of FIG. 3, and FIG. 4B is a diagram showing states of control signals and the like during table setting and table access. Is.

FIG. 5 is a diagram showing a configuration of a first application type (application type 1) of the present invention.

6 (a) and 6 (b) are diagrams showing effects of the applied type 1 (FIG. 5), respectively.

FIG. 7 is a diagram showing a configuration of an example (specific example) of an applied type 1 (FIG. 5).

8A to 8C are diagrams showing effects of the embodiment of FIG. 7, respectively.

FIG. 9 is a diagram showing a configuration of a second application type (application type 2) of the present invention.

FIG. 10 (a) is an example (specific example) of application type 2 (FIG. 9).
, (B) is a diagram showing the effect of the present embodiment, and (c) is a diagram showing the setting contents of the address table.

FIG. 11 is a diagram showing a configuration of a third application type (application type 3) of the present invention.

12A is a diagram showing a configuration of an embodiment (specific example) of the application type 3 (FIG. 11), and FIG. 12B is a diagram showing contents of an address table.

FIG. 13 is a timing chart showing an operation example of the embodiment of FIG.

FIG. 14 is a diagram for explaining the effect of the embodiment of FIG.

FIG. 15 is a diagram showing a configuration of a fourth application type (application type 4) of the present invention.

16A is a diagram showing the configuration of an embodiment (specific example) of the application type 4 (FIG. 15), and FIG. 16B is a transfer source (source) and a transfer destination (destination) of this embodiment. FIG. 3C is a diagram showing the relationship between the images of FIG. 3C and FIG. 3C is a diagram showing an example of the contents of the table and the convolution coefficient.

17 is a diagram showing a configuration of a convolution operation unit 130 of FIG.

FIG. 18 is a diagram showing a configuration of a fifth application type (application type 5) of the present invention.

FIG. 19 is a diagram showing a configuration of a sixth application type (application type 6) of the present invention.

FIG. 20 is a diagram showing a configuration of an example (specific example) of an applied type 6 (FIG. 19).

21 (a) and 21 (b) are diagrams showing effects of the embodiment of FIG. 20, respectively.

FIG. 22 is a diagram showing a configuration of a seventh application type (application type 7) of the present invention.

23A is a diagram showing a configuration of an applied type 7; FIG.
3 is a timing chart showing an example of the operation.

FIG. 24 is a diagram showing an example of effects of the embodiment of FIG. 23.

FIG. 25 is a diagram showing a schematic configuration of a photo trimming device.

[Explanation of symbols]

 1 dot counter 2 line counter 3 horizontal address table memory 4 vertical address table memory 5 address generation circuit 6 image memory

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 5/00 550 T 8121-5G H04N 1/21 7232-5C 1/387 4226-5C

Claims (13)

[Claims] 1. A memory to be accessed, wherein one address is determined by an address in a first direction and a second address in a direction intersecting the first direction, and the first direction. 1st storing the access address of
Address table memory, and a second address memory that stores the access address in the second direction.
Address table memory, and a count value is updated every time the access address of the memory to be accessed in the first direction is changed, and the first address table memory is addressed by the count value to access the access target memory. A first counter for generating an access address of the memory in the first direction, and a count value is updated each time the access address of the memory in the second direction is changed. And a second counter that addresses the second address table memory to generate an access address of the memory to be accessed in the second direction. 2. A data processing circuit using a memory according to claim 1, wherein both the first address table memory and the second address table memory are RAMs capable of rewriting table data. 3. A memory to be accessed is an image memory of a bitmap format capable of writing / reading image data, and the first counter operates by a dot clock corresponding to one pixel of the image, and the second counter The counter operates in accordance with a line clock corresponding to one line of an image. The first address table memory stores horizontal access addresses, and the second address table memory stores vertical access addresses. A data processing circuit using the memory according to claim 1. 4. The operation clock input to the first and second counters, the addressing of the first and second address table memories by the output of these counters, and the output of these address table memories.
At least one of the routes of the two systems leading to the access of the memory to be accessed by the address data of the system is provided with an intersection of the routes of the two systems, and the use of the intersection enables the processing of each route to be performed. The data processing circuit using the memory according to claim 1, wherein the flows can be switched to each other. 5. A memory to be accessed, wherein one address is determined by an address in a first direction and a second address in a direction intersecting the first direction, and the first direction. 1st storing the access address of
Address table memory, and a second address memory that stores the access address in the second direction.
Address table memory, and a count value is updated every time the access address of the memory to be accessed in the first direction is changed, and the first address table memory is addressed by the count value to change the first address table memory to the first address table memory. A first counter for generating an access address in the second direction, and a count value is updated each time the access address in the second direction of the memory to be accessed is changed, and the second address table memory is updated by the count value. And a second counter for addressing a second address for generating an access address in the second direction and the first and second address table memories respectively. The first and second output from the table memory
Memory having first and second arithmetic processing circuits for receiving access addresses in the direction of, and performing arithmetic processing on these access addresses, thereby generating actual access addresses of the memory to be accessed. Data processing circuit using. 6. The first and second address table memories are RAMs capable of rewriting table data, and the first and second arithmetic processing circuits arbitrarily set coefficients used for arithmetic processing. 6. The memory according to claim 5, which has a function capable of performing, and updates the coefficient of the operation of the first and second arithmetic processing circuits in response to the rewriting of the contents of the first and second address table memories. The data processing circuit that was used. 7. A memory to be accessed, wherein one address is determined by an address in a first direction and a second address in a direction intersecting the first direction, and the first direction. 1st storing the access address of
Address table memory, and a second address memory that stores the access address in the second direction.
Address table memory, a third address table memory that stores different table data different from the contents of the table data stored in the first address table memory, and a memory that is the access target. The count value is updated each time the access address in the first direction is changed, and the first address table memory and the third address table memory are alternately addressed with some association by the count value, and the access is performed. A first counter that generates an access address in the first direction of the target memory, and a count value that is updated each time the access address of the second target memory in the second direction is changed. Addressing the second address table memory with And a second counter for generating an access address of the second direction of the memory is Seth target, the data processing circuit using a memory. 8. A memory to be accessed, wherein one address is determined by an address in a first direction and a second address in a direction intersecting the first direction, and the first direction. 1st storing the access address of
Address table memory, and a second address memory that stores the access address in the second direction.
Address table memory, and a count value is updated every time the access address of the memory to be accessed in the first direction is changed, and the first address table memory is addressed by the count value to access the access target memory. A first counter for generating an access address of the memory in the first direction, and a count value is updated each time the access address of the memory in the second direction is changed. A second counter for addressing the second address table memory to generate an access address of the memory to be accessed in the second direction; and data output by accessing the memory to be accessed On the other hand, a memory having a processing circuit for performing a predetermined process is used. Data processing circuit. 9. The data processing circuit using a memory according to claim 8, wherein the processing circuit is a spatial filter that filters the data output from the memory to be accessed to change the spatial frequency. 10. A memory to be accessed, wherein one address is determined by an address in a first direction and a second address in a direction intersecting the first direction, and the first direction. 1st storing the access address of
Address table memory, and a second address memory that stores the access address in the second direction.
Address table memory, a third address table memory that stores different table data different from the contents of the table data stored in the first address table memory, and a memory that is the access target. The count value is updated each time the access address in the first direction is changed, and the first address table memory and the third address table memory are alternately addressed with some association by the count value, and the access is performed. A first counter that generates an access address in the first direction of the target memory, and a count value that is updated each time the access address of the second target memory in the second direction is changed. Addressing the second address table memory with A second counter that generates an access address of the memory to be accessed in the second direction; and data that is output when the memory to be accessed is accessed to change the spatial frequency. A data processing circuit using a memory having a spatial filter. 11. A transfer source memory, in which one address is determined by an address in a first direction and a second address in a direction intersecting the first direction, and a memory of this transfer source. A first address table memory storing the first-direction access address of the second address table memory, a second address table memory storing the second-direction access address of the transfer source memory, Like the memory of the transfer source, one address is the first address
The transfer destination memory, which is determined by the address in the direction and the second address in the direction intersecting with the first direction, and the access address in the first direction for the transfer destination memory are stored. A third address table memory, a fourth address table memory storing an access address of the transfer destination memory in the second direction, and a fourth address table memory of the transfer source memory and the transfer destination memory in the first direction. The count value is updated each time the access address is changed, the first and third address table memories are addressed by the count value, and the access addresses of the transfer source memory and the transfer destination memory in the first direction are determined. A first counter to be generated and a count value for each change of the access address in the second direction of the transfer source and transfer destination memories A second counter for updating and addressing the second and fourth address table memories according to the count value to generate access addresses in the second direction of the transfer source memory and the transfer destination memory, respectively. , A data processing circuit using a memory. 12. A plurality of memories, one address of which is determined by an address in a first direction and a second address in a direction intersecting with the first direction, a common address bus and a common data bus. And the operation modes of the plurality of memories are independently controllable by the CPU. Furthermore, as a result of the control of the operation mode by the CPU, A first address table memory that stores the access address in the first direction, and a second address table memory that stores the access address in the second direction for the memory that is the transfer source thereof, As a result of the control of the operation mode of the CPU, a third address table storing the access address in the first direction for the memory to be the transfer destination is stored. Memory and a fourth address table memory that stores the access address of the transfer destination memory in the second direction, and the change of the access address of the transfer source and transfer destination memories in the first direction A first count value is updated every time, and the first and third address table memories are addressed by the count value to generate access addresses in the first direction of the transfer source memory and the transfer destination memory, respectively. Counter and the count value is updated each time the access addresses of the transfer source memory and the transfer destination memory in the second direction are changed, and the second and fourth address table memories are addressed by the count value and transferred. A second generating access address in the second direction for each of the source and destination memories And a data processing circuit using a memory having a counter. 13. A data processing circuit using a memory according to claim 1, which is used for processing image data in a photographic film trimming device.