JPS6029855A - Address control system - Google Patents

Abstract

PURPOSE:To handle two-dimensional data at a high speed and alter easily the dimension such as a longitudinally long, a laterally long, and a square shape, etc., by performing DMA (dynamic memory access) transfer in an optional rectangular area in a linear memory by one-time parameter setting and starting. CONSTITUTION:Data DELTA(x), P(x), P(y), and DELTA(y) on an image are inputted from a bus 16 to initial value registers 5-7 and a counter 14. The starting point of the image is indicated with the initial value of the data P(x) and P(y), the data DELTA(x) is counted 10 with a clock signal, and the address of the data P(x) is counted 11; once X-directional DMA is completed, an Y-directional shift is made, and the X-directional DMA is repeated until the DELTA(y) counter 14 attains to a specific value. Then, the X and Y position and ratio X/Y are indicated to a shifting circuit 8 and a decoder 13 with the output of an X and Y size control register 9. The outputs of P(x) and P(y) address counters 11 and 12 and the output of a decoder 13 are multiplexed 15 to alter the longitudinal/lateral ratio of a rectangle at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention mainly relates to a memory device having a one-dimensional structure for storing image data, and in particular to a method for transferring image data having a two-dimensional data structure from the memory device. When performing this, two-dimensional Guinaminok memory by attlesing in
The present invention relates to an address control method that allows access and allows variable definition of the capacity of memory resources in the X and Y directions.

(b) Prior art and problems Conventionally, in a memory device with a -dimensional memory structure, addresses are given sequentially in the vertical direction, and data is written in the horizontal direction in accordance with the horizontal capacity of the memory. /In order to handle image data that originally has a two-dimensional data structure in a memory device that writes/reads data in order to specify the address in the edge direction by reading, two-dimensional image data is required. By rask scanning, −
It is dimensionalized and stored in memory, and a -dimensional address space (
The method used was to perform address calculations within the range of addresses that can be referenced by the program and treat image data two-dimensionally, which placed a heavy burden on address calculations. FIG. 1 is a diagram illustrating the operation of storing two-dimensional data in a one-dimensional memory. In memory 1, from the origin 0°0 of memory 1, P(x) in the horizontal axis X direction, P in the vertical axis Y direction (Δ(x) in the X direction and Δf in the Y direction at the yl position
When storing image data 2 with a size of yl,
Scanning is performed in the X direction from the address P (y) in the Y direction of memory 1, and calculates the position of P (xi) from the starting point 0,
P (Write continuous data by Δ(Xl from Xl,
Next, the address P in the Y direction (+1 yl and the starting point O
From P (calculate the position of Xl, from P(×) to Δ(×)
The operation is completed by repeating the operation of writing consecutive data by Δ(yJ) and scanning the range of Δ(yJ).

Therefore, it is necessary to calculate the position of P(x) on one scanning line every time, and since the data in the X direction is address discontinuous, -
This method has disadvantages in that it is impossible to transfer data continuously by activating dynamic memory access once, it requires dynamic memory access activation in rask units, and the burden of address calculation is heavy.

There is also a method of making the memory structure itself two-dimensional, but this method has drawbacks such as the memory control circuit becomes complicated, the amount of hardware increases, and it is not economical.

(C) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks, and to facilitate the handling of image data having a two-dimensional data structure in a memory device having a normal one-dimensional address structure. By specifying the X and Y coordinates of the data and the size in the X and Y directions, two-dimensional dynamic memory access is possible by starting - times, and the setting of the memory capacity in the x and Y directions is variable. The object of the present invention is to provide an all-res control method that can handle image data of various sizes.

(d) Structure of the Invention The structure of the present invention is that in a device that accesses a memory having an m-bit address and transfers data in an idle rectangular area, the lower or upper n bits of the m-bit address are X direction address, upper or lower m - n bits as Y
X-direction control that generates the X-direction and Y-direction addresses of the data to be transferred by assigning them as addresses and seizing the X-direction and Y-direction start addresses and the X-direction and Y-direction transfer sizes of the rectangular area, respectively. means and a Y-direction control means, and the number of bits n representing the X-direction address is provided.
Or, do not represent the address in the Y direction, but use the number of bits rn-n to
Means for synthesizing the X-direction address and the Y-direction address generated by the direction address control means and the Y-direction IS address control means is provided, and the memory is accessed using this synthesized address. .

(e) Embodiments of the Invention The present invention is applicable to dynamic memory access transfer of one-dimensional image data stored in a memory having a -dimensional address structure, as described above with reference to FIG. In order to solve the problem that it is necessary to activate dynamic memory access in the rask position and transfer image data in units of rask, the memory atrus is divided into X and Y, and dynamic memory access in the X direction is performed. A circuit is provided that automatically writes Y each time the data is completed, so that two-dimensional data with discontinuous addresses can be transferred with a single activation of dynamic memory access. Furthermore, by making the X and Y division positions of the address variable, the two-dimensional space can be set within the memory capacity in units of powers in the X direction. Also, the lower n bits of the m-bit address of a memory with an m-bit address
When ・is assigned to the address in the X direction, the upper m −n
Pi1- is assigned to the Y direction address, and when the upper n bits are assigned to the X direction address, the lower m−n bits are assigned to the Y direction address.

FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention. For example, if the memory capacity is 64 and hide, 16
The lower n bits of the address line of Binoto are moved in the X direction.
address, and the remaining 16-n Hiso 1- is used as the address in the Y direction. Consider the transfer of a rectangular area f;B such as image data 2 shown in FIG. In order to instruct the address for transferring the image data 2 at the time of starting the memory access, the n bits are sent to the X, Y size control register 9 via the data bus 16, and P(×
) Set the transfer start address P tx+ in the initial value register 6, and set the transfer start address P (yl) in the initial value register 7. Also, set the transfer start address P (yl) in the initial value register 5. Set Δ(X) indicating the size in the X direction of the image data 2 to be transferred to the counter 14, and Δ(yl indicating the size in the Y direction of the image data 2 to be transferred to the counter 14. P (y) initial value register The transfer start address P (yl is the transfer start address P in the shift circuit 8
, shifted by n bits to the left by the n placed in the Y size control register 9 and placed in the P (yl address counter 2. That is, the Y address constitutes the upper 16-n bits 1- of the memory addresses. In order to do that, P (yl
Ptyi is set to the upper 16-n bits of the address counter 12.
Set the Y address stored in initial value register 7. Δ(Xl initial value register 5 is set!- Δ(×)
is set in the Δ(×) counter 10, and the transfer start address P(Xl
is set to 1- in the P(x) address counter 11. n
Since the range of is O≦n≦15, P(
×) Address counter 11, P (y) Address counter 12 has a capacity of 16 bits.

The clock enters Δ(Xl counter 10 and P(×) address counter 11, and Δ(
x) counter 10 is incremented by -1, and P(x) address counter 11 is incremented by +1. Immediately, the Δ(ni) counter 10 monitors the completion of one scan of the rask scan that scans the range of Δ(Xl of the image data 2, and the Addresses for each high 1 to 1 are not shown. Δ(Xl counter 10 sends out a carry signal when the size 8 (X) in the X direction of image data 2 that has been secessed 1 - becomes zero, and Δ(Xl initial value Δ from register 5
(Add Δ(×) to the Xl counter 10 again by seven times, and P (
From Xl initial value register 6 to P(x) address counter 1
1, set the transfer start address P(x) by 7, add 1 to the value of P(yl initial value register 7, and decrement the value of Δ(yl counter 14 by 1. The value is shifted n hits to the left by the shift circuit 8 and n bits set in the X, Y size control register 9, and then sent to the P(yl address counter 12).

P (The output of the yl address counter 12 serves to make the image data described above continuous at addresses in the Y direction. The n bits set in the X, Y size control register 9 are The count values of the P(x) address counter 11 and the P(yl address counter 12) are also sent to the multiplexer 15.

FIG. 3 shows a detailed circuit diagram of multiplexer 15. P(
×) Each bit from lower via h x O to upper hino l-x 15 of address counter 11 is in order xO is AN
D circuit 21, xl to AND circuit 23, x2 to A, N
D circuit 25, xl4 to AND circuit 27, xl5 to A
The signals are sent to the ND circuit 29, respectively.

P (The lower bits yO to yl5 of the yl address counter 12 are sequentially input to the AND circuit 22,
yl is connected to the ANDI circuit 24, y2 is connected to the ANI) circuit 26, yl4 is connected to the AND circuit 28, and yl5 is connected to the AND circuit 30.
will be sent to each. Each bit from the lower bit SO to S15 of the decoder 13 is sequentially connected to the AND circuit 21 and N.
OT circuit 16, Sl is AND circuit 23 and NOT circuit 1
7, S2 is connected to the AND circuit 25 and NOT circuit 18;
4 is connected to AND circuit 27 and NOT circuit 19, S15 is connected to AN
The signals are sent to the D circuit 29 and the NOT circuit 20, respectively.

The output of NOT circuit 16 is sent to AND circuit 22, the output of NOT circuit 17 is sent to AND circuit 24, the output of NOT circuit 18 is sent to AND circuit 26, the output of NOT circuit 19 is sent to AND circuit 28, and the output of NOT circuit 20 is sent to AND circuit 22. The signals are sent to the AND circuit 30, respectively. Therefore, the n bits (X
For example, if the bits representing the address are 3 bits, the lower bins 1 to sQ to 52 of the decoder 12 are 1'' to select xOlxl and x2 of the P(x) address counter 11.
Therefore, the AND circuits 21, 23, and 25 are turned on, and the lower three pins 1-xO to x2 of the P(x) address counter 11 are connected to the terminal AO through the OR circuits 31, 32, and 33.
to A2, respectively. Remaining terminals A3 to A1
5 is from y3 to y of P fyl address counter 12.
Each bit up to 15 is sent out by an AND circuit 28, 30, etc. via an OR circuit 34, 35, etc. Δfy) counter 14
is Δ(y1
If you scan for a minute, it becomes zero. When the Δ(yl counter 14 becomes zero, a carry signal is sent to terminal B and the memory access is terminated. Because it operates as described above,
Once the Guinamisoku memory access is started, image data 2 can be transferred from the address P (Xl, P fyl position) by consecutive addresses sent to terminals AO to A15. Also, depending on the value of n, the image data 2 can be transferred in the memory by Two-dimensional space can be set arbitrarily.

(f) As described in detail, the present invention is capable of performing Guinaminok memory access transfer of an arbitrary rectangular area in a one-dimensional memory by setting and starting up the image data, etc. Information with a two-dimensional data structure can be handled at high speed. Furthermore, since the definition of the two-dimensional logical space can be varied by changing the dividing position of the X and Y addresses, that is, the n mentioned above, the two-dimensional space can be arbitrarily set according to the shape of the image data, such as vertically long, horizontally long, square, etc.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the operation of storing two-dimensional data in a one-dimensional memory, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a detailed circuit diagram of the multiplexer 15. 5 is a Δ(×) initial value register, 6 is a P (X) initial value register, 7 is a P (yll initial value register, 8 is a shift circuit, 9 is an X1Y size control register, 10 is a Δ(×) counter, 11 is a P (Xl address counter 12 is P
fyl address counter, 13 is decoder, 14 is Δ
fyl counter 15 is a multiplexer.

Claims (1)

[Claims] In a device that accesses a memory having an m-bit address and transfers data in an arbitrary rectangular area, the lower or upper n bits of the m-bit address are used as the X-direction address, and the upper or lower m - The rl bit and bit are assigned as Y addresses, the start addresses in the X and Y directions of the rectangular area and the transfer sizes in the X and Y directions are set, and the X and Y directions addresses of the data to be transferred are issued. X-direction address control means and Y-direction control means are provided, and the X-direction address control means and Y-direction-7 address control means are provided based on the number of focus n, which does not represent the X-direction address, or the number of bits rn-ri, which does not represent the Y-direction address. An address control method characterized in that means is provided for synthesizing an X-direction address and a Y-direction address generated in the above, and a memory is accessed using the synthesized address.