JPS61228582A - Picture processor - Google Patents

Abstract

PURPOSE:To perform the transfer and arithmetic of picture data at a high speed by applying the arithmetic to the data received as an access from a memory connected to a computer bus and leading this data to the memory in response to the mode information given from the memory. CONSTITUTION:A DMA controller for picture processing is connected to a bus B of a computer via a bus interface 1. Then the information on the transfer mode and the information on the arithmetic mode and the load coefficient are written on the register groups 8 and 9 respectively from the computer. While the data contents of a look-up table 12 are written on the table 12. A timing controller 6 gives the timing signal to an address generator 7, and the generator 7 produces the address signal to give access to a memory by the 2-dimensional scan in response to the contents of the group 8. The picture signal underwent arithmetic through an arithmetic unit 10 is led to the memory connected to the bus B by the signal produced from the generator 7. Thus the picture data can be transferred and calculated at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an image processing device that can transfer a large amount of image data and perform calculations at high speed.

(Prior Art) In recent years, advances in LSI technology have made it possible to produce high-performance microprocessors and large-capacity memories in small sizes and at low cost, making it possible to construct high-performance computer systems at low cost.

However, no matter how sophisticated the functions are, the processing speed of inexpensive devices is insufficient when applied to image processing. In other words, since image data generally uses two-dimensional data, the amount of data is enormous (for example, one pixel consists of 8
(1M byte in the case of a bit gradation of 1024 pixels/024 pixels per screen), and conventional sequential processing by a computer required a large amount of processing time. Conventionally, as a countermeasure against this problem, a high-speed bus dedicated to image processing was provided and hardware dedicated to image processing was connected to this high-speed bus to speed up the processing. With this configuration, compared to sequential processing by a normal computer, it is possible to speed up the processing by about two to three orders of magnitude. However, the dedicated image processing hardware configured in this manner has the disadvantage that it can only be applied to specific dedicated systems and cannot be used in general microcomputer systems.

On the other hand, there is already a DMA (
Direct Memory Access) controllers have been developed as peripheral LSIs for various microprocessors. These DMA controllers can be easily connected to a microprocessor bus and can perform data transfers that are one to two orders of magnitude faster than normal program transfers. However, since it only has an access function by one-dimensional scanning, it is impossible to transfer data only within an arbitrary rectangular area in the image memory, and it does not have arithmetic functions, so it is impossible to transfer data within an arbitrary rectangular area in the image memory. It was also impossible to perform calculations.

<Objects> An object of the present invention is to eliminate the drawbacks of the prior art described above, to be connectable to a general-purpose computer bus, and to perform two-dimensional scanning of an image memory located in a one-dimensional address space of a computer. An object of the present invention is to provide an image processing device that can transfer image data and perform calculations at high speed.

<Example> Hereinafter, one example according to the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention.

An image processing DMA controller, which is an image processing device, shown in FIG. 1 is connected to a bus B of a computer via a bus interface l. The bus interface l is designed to satisfy the specifications of the target computer bus B, and consists of circuits such as an address bus buffer 2, a data bus buffer 3, a control bus buffer 4, and a control bus logic 5. be done. Most of the address bus buffer 2, data bus 0 buffer 13, and control bus buffer 4 are capable of bidirectional input/output and tristate output, and are capable of bidirectional input/output and tristate output.
Designed to function as a mask or bus slave.

This DMA controller for image processing is usually a bus slave, and is connected to the transfer mode from the host computer.
It receives and receives various data information and command information such as operation mode, weight coefficient, lookup table contents, etc. Note that information regarding the transfer mode is written to the register group 8, information regarding the calculation mode and weighting coefficient is written to the register group 9, and data contents of the lookup table are written to the lookup table 12 via the bus interface l.

This image processing DMA controller starts its operation upon receiving a transfer start command from the host computer, and becomes the bus master after confirming that it has acquired the right to use the bus. When the bus mask completes the data transfer and operation specified in advance by the host computer, it issues an interrupt signal via the bus interface I or sets an end flag, and becomes the bus slave again.

In the circuit shown in FIG. 1, the timing controller 6 provides timing signals necessary for the address generator 7 to generate addresses, and also synchronizes the address generator 7 and the bus interface 1. The address generator 7 is a circuit that generates address information for sequentially accessing the memory by two-dimensional scanning in accordance with the contents of the register group 8.

2 given to the address generator 7 from the register group 8
The parameters for dimensional scanning are as follows.

Now, as shown in FIG. 2, on a screen having a horizontal width X, let PQ be the start address at the upper left of the target rectangular area A, ΔX be the width in the horizontal direction, and ΔY be the width in the vertical direction. Generally, when allocating image memory in the one-dimensional address space of a computer, the address of the pixel in the upper left corner is set as the minimum address, and the address is increased as it moves one pixel to the right in the horizontal direction, like mask scanning, and When scanning is completed, addresses are assigned in the same manner starting from the leftmost pixel of the next line immediately below, and the same address setting is performed in FIG. 2 as well. In this case, the i-th point in the horizontal direction from PQ in FIG.

The address of the j-th point P (i, j) in the vertical direction is PQ+, X+i (0:1:ΔXI O!
,! It is given as (b). Here, address generator 7
is provided with a simple arithmetic function, and the above F'Q written in advance from the host computer to register group 8
, x+ΔX, ΔY, etc., address information for scanning an arbitrary rectangular area is generated at high speed.

Next, the register group 9, arithmetic unit 10, accumulator 11, and look-up table 12 shown in FIG. 1 are all used for calculations associated with data transfer.

As described above, various information regarding operations (for example, operation mode information, load coefficients, conditions, etc. of arithmetic operations or logical operations to be executed) is written in the register group 9 in advance from the host computer. and arithmetic unit lO
performs a predetermined operation on the data read from the image memory according to the output information of the register group 9. The accumulator 11 has a function of accumulating the results of this calculation, and is used for calculations between multiple images. Further, the look-up table 12 is used, like the arithmetic unit 10, when performing arithmetic operations on transferred data, and is particularly useful when performing non-linear processing. Lookup table 12 is high speed RA
This can be easily achieved by using M memory. However, the contents of the lookup table must be written in advance from the host computer. If the lookup table processing is routine, it is also possible to use ROM instead of RAM.

Here, we will explain the various functions described above as an image processing DMA.
The operating modes of the controller can be summarized as follows.

+1+ Image clear mode This is an operation mode in which constants are written to all memories within a given rectangular area, and the DMA controller only writes to the memory and does not read. Note that if some function generation means is provided inside the image processing DMA controller, it becomes possible to write not only constants but also functions to the memory.

(2) Scanning mode This is an operation mode in which all memories within a given rectangular area are read and the accumulated results of specified operations are left in an accumulator. In this mode, the DM for image processing
The A controller only reads from memory.

(3) Transfer calculation mode In this mode, two rectangular areas are given, a calculation is performed on the contents read from the memory in one area, and the result is written to the corresponding memory in the other area. In this case, various nonlinear operations can be performed using lookup table processing. For example, gradation correction threshold processing can be mentioned. Note that the two rectangular areas may be the same, in which case the input screen and the output screen will match.

(4) Inter-screen calculation mode Given a plurality of input rectangular areas (J, S2+..., Sn) and output rectangular areas, Sl, S2...・・）S
An operation is performed on the contents read from the respective corresponding areas of , and the cumulative result is written to the corresponding area of D. This mode is effective for calculations between two images, color distance calculations, etc. Sl.

s2. ...+S1 and D may be the same, and can also be used for so-called raster operations.

Next, the processing speed of the entire system when using the image processing DMA controller will be explained. As shown in Figure 3, the image processing DMA controller is used by being connected to a bus to which a computer's CPU (central processing unit) and RAM (memory) are respectively connected, and data transfer is performed via this bus. It will be done. In addition, the above image processing D
Inside the MA controller, various calculations are performed at high speed by dedicated hardware. Therefore, in FIG. 3, the data transfer and calculation speeds of the entire system when using the image processing DMA controller described above are mainly determined by the data transfer speed determined by the bus specifications or the access time of the memory used. . However, the above-mentioned image processing DMA controller has a dedicated two-dimensional address generation function and arithmetic function as hardware, which makes it 1 to 2 times faster than the sequential processing by a conventional computer.
It becomes possible to speed up processing by orders of magnitude.

<Effects> According to the present invention described above, the conventional general computer
Transfer image data just by connecting to the bus.

Image conversion, calculations between one image, etc. can be performed at very high speed.゛

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an embodiment of an image processing device according to the present invention, FIG. 2 is an explanatory diagram for explaining addresses of pixels in a rectangular area of memory, and FIG. 8 is an overall system configuration diagram. shows. In the figure, 1... bus interface 9, 2... address bus buffer, 8... data bus buffer 1, 4...
Core: Address generator, 8: Register group, 9.
... Register group, 10 Arithmetic unit, 11... Accumulator. 12... Lookup table agent Patent attorney Aihiko Fukushi (and 2 others) Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. A processing device connected to a computer bus to which a central processing unit and a memory of a computer are respectively connected, comprising address generation means for generating an address signal for the memory, and bus signal generation means. a calculation means for performing an operation on the data accessed from the memory; a storage means for storing the calculation result; and introducing the calculation result into the memory using the address generation means and the bus signal generation means. An image processing device characterized by comprising: introduction means.